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參數(shù)資料
| 型號： | 9ZX21501CKLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9ZX SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-64 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 173K |
| 代理商： | 9ZX21501CKLF |
IDT
15-Output Differential Zbuffer for PCIe Gen2/3 and QPI
1683A - 08/03/10
9ZX21501C
15-Output Differential Zbuffer for PCIe Gen2/3 and QPI
7
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
CLK_IN, DIF[x:0]
tSPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
-100
0
100
ps
1,2,4,5,8
CLK_IN, DIF[x:0]
tPD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
2.5
3.5
4.5
ns
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSPO_PLL
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
-50
0
50
ps
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSPO_BYP
Input-to-Output Skew Varation in Bypass mode
across voltage and temperature
-350
0
350
ps
1,2,3,5,8
CLK_IN, DIF[x:0]
tDTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
35
ps
(rms)
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode
15
75
ps
1,2,3,5,8
DIF{x:0]
tSKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
37
65
ps
1,2,3,8
PLL Jitter Peaking
jpeak-hibw
LOBW#_BYPASS_HIBW = 1
0
1.3
2.5
dB
7,8
PLL Jitter Peaking
jpeak-lobw
LOBW#_BYPASS_HIBW = 0
0
0.8
2
dB
7,8
PLL Bandwidth
pllHIBW
LOBW#_BYPASS_HIBW = 1
2
3
4
MHz
8,9
PLL Bandwidth
pllLOBW
LOBW#_BYPASS_HIBW = 0
0.7
1.1
1.4
MHz
8,9
Duty Cycle
tDC
Measured differentially, PLL Mode
45
50
55
%
1
Duty Cycle Distortion
tDCD
Measured differentially, Bypass Mode
@100MHz
-2
0
2
%
1,10
PLL mode
41
50
ps
1,11
Additive Jitter in Bypass Mode
20
50
ps
1,11
Notes for preceding table:
6.t is the period of the input clock
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8. Guaranteed by design and characterization, not 100% tested in production.
9 Measured at 3 db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode
11 Measured from differential waveform
Jitter, Cycle to cycle
tjcyc-cyc
1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device
5 Measured with scope averaging on to find mean value. DIF IN slew rate must be matched to DIF output slew rate.
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9ZX21501CKLFT | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9ZX21901B | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:19-Output Differential Zbuffer for PCIe Gen2/3 and QPI |
| 9ZX21901BKLF | 功能描述:時鐘緩沖器 HIGH PERF. ZDB DB190 0Z w/External Fdbk RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9ZX21901BKLFT | 功能描述:時鐘緩沖器 HIGH PERF. ZDB DB190 0Z w/External Fdbk RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9ZX21901C | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:19-Output Differential Zbuffer for PCIe Gen2/3 and QPI |
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