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參數(shù)資料
| 型號： | 9UMS9610CKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48 |
| 封裝： | 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 134K |
| 代理商： | 9UMS9610CKLFT |
IDTTM/ICSTM PC MAIN CLOCK
1336—06/01/09
ICS9UMS9610
PC MAIN CLOCK
12
Byte
4
CPU PLL M/N Register
Bit(s)
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
CPU N Div8
N Divider Prog bit 8
RW
X
Bit 6
CPU N Div9
N Divider Prog bit 9
RW
X
Bit 5
CPU M Div5
RW
X
Bit 4
CPU M Div4
RW
X
Bit 3
RW
X
Bit 2
CPU M Div2
RW
X
Bit 1
CPU M Div1
RW
X
Bit 0
CPU M Div0
RW
X
Byte
5
CPU PLL M/N Register
Bit(s)
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
CPU N Div7
RW
X
Bit 6
CPU N Div6
RW
X
Bit 5
CPU N Div5
RW
X
Bit 4
CPU N Div4
RW
X
Bit 3
CPU N Div3
RW
X
Bit 2
CPU N Div2
RW
X
Bit 1
CPU N Div1
RW
X
Bit 0
CPU N Div0
RW
X
Byte
6
DOT96 PLL M/N Register
Bit(s)
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
DOT N Div8
N Divider Prog bit 8
RW
X
Bit 6
DOT N Div9
N Divider Prog bit 9
RW
X
Bit 5
DOT M Div5
RW
X
Bit 4
DOT M Div4
RW
X
Bit 3
DOT M Div3
RW
X
Bit 2
DOT M Div2
RW
X
Bit 1
DOT M Div1
RW
X
Bit 0
DOT M Div0
RW
X
Byte
7
DOT96 PLL M/N Register
Bit(s)
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
DOT N Div7
RW
X
Bit 6
DOT N Div6
RW
X
Bit 5
DOT N Div5
RW
X
Bit 4
DOT N Div4
RW
X
Bit 3
DOT N Div3
RW
X
Bit 2
DOT N Div2
RW
X
Bit 1
DOT N Div1
RW
X
Bit 0
DOT N Div0
RW
X
The decimal representation of M
and N Divider in Byte 4 and 5 will
configure the CPU VCO
frequency. Default at power up
= latch-in. VCO Frequency =
14.318 x [NDiv(11:0)] /
[MDiv(5:0)]
M Divider Programming
bit (5:0)
M Divider Programming
bit (5:0)
The decimal representation of M
and N Divider in Byte 6 and 7 will
configure the DOT VCO
frequency. VCO Frequency =
14.318 x [NDiv(11:0)] /
[MDiv(5:0)]
N Divider Programming Byte7 bit(7:0) and
Byte6 bit(7:6)
The decimal representation of M
and N Divider in Byte 6 and 7 will
configure the DOT VCO
frequency. VCO Frequency =
14.318 x [NDiv(11:0)] /
[MDiv(5:0)]
N Divider Programming Byte5 bit(7:0) and
Byte5 bit(7:6)
The decimal representation of M
and N Divider in Byte 4 and 5 will
configure the CPU VCO
frequency. Default at power up
= latch-in. VCO Frequency =
14.318 x [NDiv(11:0)] /
[MDiv(5:0)]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9UMS9610CKLF | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48 |
| 9UMS9633BFILFT | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9UMS9633BKILFT | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48 |
| 9UMS9633BFLFT | OTHER CLOCK GENERATOR, PDSO48 |
| 9ZX21501CKLFT | 9ZX SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9UMS9633 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE |
| 9UMS9633BFILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9UMS9633BFILFT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9UMS9633BFW3LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE |
| 9UMS9633BKILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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