參數(shù)資料
型號： 9S12D32DGV1
英文描述： 9S12DGDJ64DGV1 Device Guide. also covers 9S12D64. 9S12A64. 9S12D32. and 9S12A32 devices
中文描述： 9S12DGDJ64DGV1設(shè)備指南。也包括9S12D64。 9S12A64。 9S12D32。和9S12A32設(shè)備
文件頁數(shù)： 55/126頁
文件大?。?/td> 1809K
代理商： 9S12D32DGV1
MC9S12DJ64 Device User Guide — V01.17
55
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.
2.3.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1
PAD15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1. It
can act as an external trigger input for the ATD1.
2.3.8 PAD[14:08] / AN[14:08] — Port AD Input Pins ATD1
PAD14 - PAD08 are general purpose input pins and analog inputs AN[6:0] of the analog to digital
converter ATD1.
2.3.9 PAD07 / AN07 / ETRIG0 — Port AD Input Pin of ATD0
PAD07 is a general purpose input pin and analog input AN0 of the analog to digital converter ATD0. It
can act as an external trigger input for the ATD0.
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0
PAD06 - PAD00 are general purpose input pins and analog inputs AN[6:0] of the analog to digital
converter ATD0.
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts
(lowpower)oscillatorisusedorwhetherPierceoscillator/externalclockcircuitryisused.Thestateofthis
pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an
external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured
on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left
floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.
相關(guān)PDF資料
PDF描述
9S12DJ64DGV1 9S12DJ64DG Device Guide. also covers 9S12D64. 9S12A64. 9S12D32 and 9S12A32 devices
9S12DJ64-ZIP_PART2 MC9S12DJ64 Users Guides. zip format. part 2
9S12DP256BDGV2 9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices
9S12DP512DGV1 9S12Dx512 Device Guide
9S12DT128BDGV1 9S12DT128B Device Guide
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9S12DJ64DGV1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12DJ64DG Device Guide. also covers 9S12D64. 9S12A64. 9S12D32 and 9S12A32 devices
9S12DP256BDGV1 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Automotive applications
9S12DP256BDGV2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices
9S12DP512DGV1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12Dx512 Device Guide
9S12DT128BDGV1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12DT128B Device Guide
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