參數(shù)資料
型號： 9LPRS511EGLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
封裝： 6.10 MM BODY, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁數(shù)： 3/19頁
文件大?。?/td> 297K
代理商： 9LPRS511EGLF
11
Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
1137—09/05/08
I2C Table: PCIEX PLL Frequency Control Register
Byte 15
Name
Control Function
Type
PWD
A/B/C/D/E/H/J
Bit 7
N Div2
N Divider Prog bit 2
RW
X
Bit 6
N Div1
N Divider Prog bit 1
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
I2C Table: PCIEX PLL Frequency Control Register (DOC0 = 0)
Byte 16
Name
Control Function
Type
PWD
A/B/C/D/E/H/J
Bit 7
N Div10
RW
X
Bit 6
N Div9
RW
X
Bit 5
N Div8
RW
X
Bit 4
N Div7
RW
X
Bit 3
N Div6
RW
X
Bit 2
N Div5
RW
X
Bit 1
N Div4
RW
X
Bit 0
N Div3
RW
X
I2C Table: PCIEX PLL Spread Spectrum Control Register
Byte 17
Name
Control Function
Type
PWD
A/B/C/D/E/H/J
Bit 7
SSP7
RW
X
Bit 6
SSP6
RW
X
Bit 5
SSP5
RW
X
Bit 4
SSP4
RW
X
Bit 3
SSP3
RW
X
Bit 2
SSP2
RW
X
Bit 1
SSP1
RW
X
Bit 0
SSP0
RW
X
I2C Table: PCIEX PLL Spread Spectrum Control Register
Byte 18
Name
Control Function
Type
PWD
A/B/C/D/E/H/J
Bit 7
SSP15
RW
0
Bit 6
SSP14
RW
X
Bit 5
SSP13
RW
X
Bit 4
SSP12
RW
X
Bit 3
SSP11
RW
X
Bit 2
SSP10
RW
X
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
I2C Table: PCIEX PLL Frequency Select Register
Byte 19
Name
Control Function
Type
PWD
A/B/C/D/E/H/J
Bit 7
Reserved
RW
1
Bit 6
Reserved
RW
0
Bit 5
Reserved
RW
0
Bit 4
FS4
Freq Select Bit 4
RW
0
Bit 3
FS3
Freq Select Bit 3
RW
0
Bit 2
FSLC
Freq Select Bit 2
RW
Latch
Bit 1
FSLB
Freq Select Bit 1
RW
Latch
Bit 0
FSLA
Freq Select Bit 0
RW
Latch
-
M Divider Programming
bit (5:0)
1
-
N Divider Programming
Byte16 bit(7:0) and Byte15
bit(7:6)
The decimal representation of M and N Divider in Byte 15
and 16 will configure the PCIEX PLL VCO frequency. Default
at power up = latch-in or Byte 0 Rom table. VCO Frequency
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
The decimal representation of M and N Divider in Byte 15
and 16 will configure the PCIEX PLL VCO frequency. Default
at power up = latch-in or Byte 0 Rom table. VCO Frequency
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
See Table 2: PCIEX PLL Frequency Selection Table
Spread Spectrum
Programming bit(7:0)
1
0
-
--
0
01
These Spread Spectrum bits in Byte 17 and 18 will program
the spread percentage of PCIEX PLL
01
0
1
-
Spread Spectrum
Programming bit(14:8)
These Spread Spectrum bits in Byte 17 and 18 will program
the spread percentage of PCIEX PLL
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參數(shù)描述
9LPRS511EGLFT 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPRS525 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:56-pin CK505 for Intel Systems
9LPRS525AFLF 功能描述:時鐘合成器/抖動清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPRS525AFLFT 功能描述:時鐘合成器/抖動清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPRS525AGILF 功能描述:時鐘合成器/抖動清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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