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參數(shù)資料
| 型號(hào)： | 9LPRS502YGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁(yè)數(shù)： | 2/29頁(yè) |
| 文件大?。?/td> | 279K |
| 代理商： | 9LPRS502YGLFT |
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IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
10
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
43
VDDSRC_IO
PWR
Power supply for SRC outputs. 1.05 to 3.3V +/-5%.
44
CPUC2_ITP/SRCC8
OUT
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
45
CPUT2_ITP/SRCT8
OUT
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
46
NC
Not Connected
47
VDDCPU_IO
PWR
Power supply for CPU outputs. 1.05 to 3.3V +/-5%.
48
CPUC1_F
OUT
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
49
CPUT1_F
OUT
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
50
GNDCPU
PWR
Ground Pin for CPU Outputs
51
CPUC0
OUT
Complement clock of low power differential CPU clock pair.
52
CPUT0
OUT
True clock of low power differential CPU clock pair.
53
VDDCPU
PWR
Power Supply 3.3V nominal.
54
CK_PWRGD/PD#
IN
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
55
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer
to Test Clarification Table.
56
GNDREF
PWR
Ground pin for crystal oscillator circuit
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相關(guān)代理商/技術(shù)參數(shù) |
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| 9LPRS502YKLFT | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR |
| 9LPRS509HGLF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS509HGLF LOGIC AND TIMING MISC - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS509HGLF Logic and Timing Misc |
| 9LPRS509PGLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LPRS509PGLFT | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK 制造商:Integrated Device Technology Inc 功能描述:64 TSSOP (LEAD FREE) - Tape and Reel |
| 9LPRS511EGLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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