參數(shù)資料
型號(hào)： 9LPR502YGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁(yè)數(shù)： 7/29頁(yè)
文件大?。?/td> 282K
代理商： 9LPR502YGLFT
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator
1124D—02/26/09
Advance Information
ICS9LPR502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
15
Datasheet
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
2, 4
Clock period
Tperiod
14.318MHz output nominal
69.82033
69.86224
ns
2, 3
Absolute min/max period
Tabs
14.318MHz output nominal
69.83400
70.84800
ns
2
CLK High Time
THIGH
29.97543
38.46654
V
CLK Low time
TLOW
29.57543
38.26654
V
Output High Voltage
VOH
IOH = -1 mA
2.4
V
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
Output High Current
IOH
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
-33
mA
Output Low Current
IOL
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
30
38
mA
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
2
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
1000
ps
2
1Edge rate in system is measured from 0.8V to 2.0V.
2 Duty cycle, Peroid and Jitter are measured with respect to 1.5V
3 The average period over any 1us period of time
4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz
NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
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