參數(shù)資料
型號(hào)： 9LPR501SGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁數(shù)： 7/21頁
文件大?。?/td> 197K
代理商： 9LPR501SGLFT
IDTTM/ICSTM
64-pin CK505 w/Fully Integrated Voltage Regulator
1118N—05/19/11
Advance Information
ICS9LPR501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
15
Datasheet
Byte 5 Clock Request Enable/Configuration Register
Bit
Pin
Name
Description
Type
0
1
Default
7
CR#_A_EN
Enable CR#_A (clk req),
PCI0_OE must be = 1 for this bit to take effect
RW
Disable CR#_A
Enable CR#_A
0
6
CR#_A_SEL
Sets CR#_A to control either SRC0 or SRC2
RW
CR#_A -> SRC0
CR#_A -> SRC2
0
5
CR#_B_EN
Enable CR#_B (clk req)
RW
Disable CR#_B
Enable CR#_B
0
4
CR#_B_SEL
Sets CR#_B -> SRC1 or SRC4
RW
CR#_B -> SRC1
CR#_B -> SRC4
0
3
CR#_C_EN
Enable CR#_C (clk req)
RW
Disable CR#_C
Enable CR#_C
0
2
CR#_C_SEL
Sets CR#_C -> SRC0 or SRC2
RW
CR#_C -> SRC0
CR#_C -> SRC2
0
1
CR#_D_EN
Enable CR#_D (clk req)
RW
Disable CR#_D
Enable CR#_D
0
CR#_D_SEL
Sets CR#_D -> SRC1 or SRC4
RW
CR#_D -> SRC1
CR#_D -> SRC4
0
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7
CR#_E_EN
Enable CR#_E (clk req) -> SRC6
RW
Disable CR#_E
Enable CR#_E
0
6
CR#_F_EN
Enable CR#_F (clk req) -> SRC8
RW
Disable CR#_F
Enable CR#_F
0
5
CR#_G_EN
Enable CR#_G (clk req) -> SRC9
RW
Disable CR#_G
Enable CR#_G
0
4
CR#_H_EN
Enable CR#_H (clk req) -> SRC10
RW
Disable CR#_H
Enable CR#_H
0
3
Reserved
RW
0
2
Reserved
RW
0
1
SSCD_STP_CRTL
(SRC1)
If set, SSCD (SRC1) stops with PCI_STOP#
RW
Free Running
Stops with PCI_STOP#
assertion
0
SRC_STP_CRTL
If set, SRCs (except SRC1) stop with
PCI_STOP#
RW
Free Running
Stops with PCI_STOP#
assertion
0
Byte 7 Vendor ID/ Revision ID
Bit
Pin
Name
Description
Type
0
1
Default
7
Rev Code Bit 3
R
X
6
Rev Code Bit 2
R
X
5
Rev Code Bit 1
R
X
4
Rev Code Bit 0
R
X
3
Vendor ID bit 3
R
0
2
Vendor ID bit 2
R
0
1
Vendor ID bit 1
R
0
Vendor ID bit 0
R
1
Byte 8 Device ID and Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
Device_ID3
R
0
6
Device_ID2
R
0
5
Device_ID1
R
0
4
Device_ID0
R
1
3
Reserved
RW
-
0
2
Reserved
RW
-
0
1
SE1_OE
Output enable for SE1
RW
Disabled
Enabled
0
0SE2_OE
Output enable for SE2
RW
Disabled
Enabled
0
Byte 9 Output Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7PCIF5 STOP EN
Allows control of PCIF5 with assertion of
PCI_STOP#
RW
Free running
Stops with PCI_STOP#
assertion
0
6
TME_Readback
Truested Mode Enable (TME) strap status
R
normal operation
no overclocking
0
5
REF Strength
Sets the REF output drive strength
RW
1X (2Loads)
2X (3 Loads)
1
4
Test Mode Select
Allows test select, ignores REF/FSC/TestSel
RW
Outputs HI-Z
Outputs = REF/N
0
3
Test Mode Entry
Allows entry into test mode, ignores
FSB/TestMode
RW
Normal operation
Test mode
0
2
IO_VOUT2
IO Output Voltage Select (Most Significant Bit)
RW
1
IO_VOUT1
IO Output Voltage Select
RW
0
IO_VOUT0
IO Output Voltage Select (Least Significant Bit)
RW
1
Vendor specific
See Device ID Table
See Table 3: V_IO Selection
(Default is 0.8V)
Revision ID
Vendor ID
ICS is 0001, binary
Table of Device identifier codes, used for
differentiating between CK505 package
options, etc.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9LPR501YGLFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
9LPR502HGLF 制造商:Integrated Device Technology Inc 功能描述:PC CLOCK, TSSOP56 - Rail/Tube
9LPR502HGLFT 制造商:Integrated Device Technology Inc 功能描述:PC CLOCK, TSSOP56 - Rail/Tube
9LPR502SGLF 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 PC MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPR502SGLFT 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 PC MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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