參數(shù)資料
型號: 9FG1901HKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72
封裝: ROHS COMPLIANT, PLASTIC, MLF-72
文件頁數(shù): 16/18頁
文件大?。?/td> 245K
代理商: 9FG1901HKLFT
IDTTM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
7
General SMBus serial interface information for the 9FG1901H
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D0
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D0
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D1
(h)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
PstoP bit
X
Byte
Index Block Write Operation
Slave Address D0(h)*
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
PstoP bit
ICS (Slave/Receiver)
Controller (Host)
X
B
yte
ACK
Data Byte Count = X
ACK
Slave Address D1(h)*
Index Block Read Operation
Slave Address D0(h)*
Beginning Byte = N
ACK
* Note: See SMBus Address Mapping (page 6), for programming SMBus Read/Write Address
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