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參數資料
| 型號： | 9FG1201HGLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁數： | 10/23頁 |
| 文件大小： | 269K |
| 代理商： | 9FG1201HGLF-T |
IDTTM/ICSTM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371E — 01/21/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
18
Electrical Characteristics - Phase Jitter
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP.
MAX
UNITS
NOTES
tjphPCIe1
PCIe Gen 1 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54,
Td=10 ns, Ftrk=1.5 MHz )
40/38
86
ps
1,2,3,5
tjphPCIe2Lo
PCIe Gen 2 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
Lo-band content
(10kHz to 1.5MHz)
1.3/1.2
3
ps rms
1,2,5
tjphPCIe2Hi
PCIe Gen 2 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
Hi-band content
(1.5MHz to Nyquist)
3.0/2.4
3.1
ps rms
1,2,5
tjphFBD1_3.2G
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
2.8/2.3
3
ps
(RMS)
1,2,5
tjphFBD1_4.8G
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
2.3/1.9
2.5
ps
(RMS)
1,2,5
Notes on Phase Jitter:
2 Device driven by 932S421BGLF or equivalent
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12
4 Hi-Bandwidth Number/Low Bandwidth Number with Spread On. Spread Off gives lower numbers.
5 Byte 8 must be properly set to meet these parameters.
1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.
Jitter, Phase
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