參數(shù)資料
型號(hào)： 9EX21501AKILF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 21501 SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64
封裝： ROHS COMPLIANT, PLASTIC, MLF-64
文件頁(yè)數(shù)： 12/15頁(yè)
文件大?。?/td> 200K
代理商： 9EX21501AKILF
IDT
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
1578—01/18/11
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
6
Datasheet
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM or TIND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
TCOM
Commmercial range
0
25
70
°C
1
TIND
Industrial range
-40
25
85
°C
1
Input High Voltage
VIH
Single-ended inputs, except SMBus,
low threshold and tri-level inputs
2
2.400
VDD + 0.3
V
1
Input Low Voltage
VIL
Single-ended inputs, except SMBus,
low threshold and tri-level inputs
GND - 0.3
0.400
0.8
V
1
IIN
Single-ended inputs, VIN = GND, VIN =
VDD
-5
5
uA
1
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up
resistors
VIN = VDD; Inputs with internal pull-
down resistors
-200
200
uA
1
Fibyp
VDD = 3.3 V, Bypass mode
33
400
MHz
2
Fipll
VDD = 3.3 V, 100MHz PLL mode
80
100.00
110
MHz
2
Fipll
VDD = 3.3 V, 133.33MHz PLL mode
120
133.33
150
MHz
2
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs, except DIF_IN
1.5
5
pF
1
CINDIF_IN
DIF_IN differential clock inputs
1.5
2.7
pF
1,4
COUT
Output pin capacitance
6
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input
clock stabilization or de-assertion of
PD# to 1st clock
0.5
1
ms
1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
33
kHz
1
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
4
10
12
clocks
1,3
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
0.2
300
us
1,3
Tfall
tF
Fall time of control inputs
5
ns
1,2
Trise
tR
Rise time of control inputs
5
ns
1,2
SMBus Input Low Voltage
VILSMB
0.4
0.8
V
1
SMBus Input High Voltage
VIHSMB
2.1
2.4
VDDSMB
V1
SMBus Output Low Voltage
VOLSMB
@ IPULLUP
0.3
0.4
V
1
SMBus Sink Current
IPULLUP
@ VOL
45
mA
1
Nominal Bus Voltage
VDDSMB
3V to 5V +/- 10%
2.7
3.3
5.5
V
1
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA Fall Time
tFSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
SMBus Operating
Frequency
fMAXSMB
Maximum SMBus operating frequency
400
100
kHz
1,5
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
4DIF_IN input
5The differential input clock must be running for the SMBus to be active. Tested at Fin=100MHz.
3Time from deassertion until outputs are >200 mV
Input Current
Input Frequency
Capacitance
Ambient Operating
Temperature
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9EX21501AKILFT 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 64-Pin VFQFPN EP T/R 制造商:Integrated Device Technology Inc 功能描述:64 MLF (LEAD FREE) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER - GEN2. 15 OUTPUTS w/2:1 INP
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9EX21501AKLFT 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 PCIE BUFFER - GEN2. 15 OUTPUTS w/2:1 INP RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
9EX21531AKLF 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 PCIE BUFFER - GEN3, 15 OUTPUTS w/2:1 INP RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
9EX21531AKLFT 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Generator Single 64-Pin MLF T/R 制造商:Integrated Device Technology Inc 功能描述:64 MLF (LEAD FREE) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER - GEN3, 15 OUTPUTS w/2:1 INP
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