參數資料
型號： 9DB1200CGLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁數： 3/14頁
文件大?。?/td> 217K
代理商： 9DB1200CGLF
IDTTM/ICSTM
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
ICS9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
11
1414E—11/04/09
SMBus Table: Frequency Select Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
HIGH_BW#
High or Low BW
RW
High BW
Low BW
Latch
Bit 6
BYPASS#/PLL
Bypass (non-PLL Mode) or PLL Mode
RW
Bypass
PLL
Latch
Bit 5
Reserved
RW
X
Bit 4
Reserved
RW
X
Bit 3
Reserved
RW
X
Bit 2
FS2
Frequency Select 2
RW
Latch
Bit 1
FS1
Frequency Select 1
RW
Latch
Bit 0
FS0
Frequency Select 0
RW
Latch
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
DIF_7
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 6
DIF_6
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 5
DIF_5
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 4
DIF_4
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 3
DIF_3
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 2
DIF_2
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 1
DIF_1
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 0
DIF_0
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Reserved
RW
0
Bit 6
Reserved
RW
0
Bit 5
Reserved
RW
0
Bit 4
Reserved
RW
0
Bit 3
DIF_11
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 2
DIF_10
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 1
DIF_9
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
Bit 0
DIF_8
Output Control (Disable = Hi-Z)
RW
Disable
Enable
1
SMBus Table: Output Enable Readback
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
OE7#
OE# Pin Readback
R
Enabled
Disabled
X
Bit 6
OE6#
OE# Pin Readback
R
Enabled
Disabled
X
Bit 5
OE5#
OE# Pin Readback
R
Enabled
Disabled
X
Bit 4
OE4#
OE# Pin Readback
R
Enabled
Disabled
X
Bit 3
OE3#
OE# Pin Readback
R
Enabled
Disabled
X
Bit 2
OE2#
OE# Pin Readback
R
Enabled
Disabled
X
Bit 1
OE1#
OE# Pin Readback
R
Enabled
Disabled
X
Bit 0
OE0#
OE# Pin Readback
R
Enabled
Disabled
X
-
Reserved
Byte 0
-
Reserved
-
Reserved
-
See FS Table
Byte 1
43,42
38,37
27,28
22,23
19,20
14,15
11,12
6,7
Byte 2
-
58,59
53,54
38,37
50,51
45,46
Byte 3
43,42
27,28
22,23
19,20
14,15
11,12
Reserved
6,7
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相關代理商/技術參數
參數描述
9DB1200CGLFT 功能描述:時鐘緩沖器 12 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1233 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Twelve Output Differential Buffer for PCIe Gen3
9DB1233AGLF 功能描述:時鐘緩沖器 12 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1233AGLFT 功能描述:時鐘緩沖器 12 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1904B 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:19 Output Differential Buffer for PCIe Gen2 and QPI
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