參數(shù)資料
型號(hào): 9DB102AGLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: PLL BASED CLOCK DRIVER, PDSO20
封裝: 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20
文件頁(yè)數(shù): 13/13頁(yè)
文件大?。?/td> 223K
代理商: 9DB102AGLF
IDTTM
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV J 01/15/10
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
9
SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5)
Pin #
Name
Control Function Type0
1PWD
Bit 7
SW_EN
Enables SMBus
Control
RW
Functions
controlled by
SMBus
registers
Functions
controlled by
device pins
1
Bit 6
RW
X
Bit 5
RW
X
Bit 4
RW
X
Bit 3
RW
X
Bit 2
RW
X
Bit 1
PLL BW #adjust
Selects PLL
Bandwidth
RW
Low BW
High BW
1
Bit 0
PLL Enable
Bypasses PLL for
board test
RW
PLL bypassed
(fan out mode)
PLL enabled
(ZDB mode)
1
SMBus Table: Output Enable Register
Pin #
Name
Control Function Type0
1PWD
Bit 7
RW
X
Bit 6
RW
X
Bit 5
RW
X
Bit 4
RW
X
Bit 3
RW
X
Bit 2
RW
X
Bit 1
RW
X
Bit 0
RW
X
SMBus Table: Function Select Register
Pin #
Name
Control Function Type0
1PWD
Bit 7
RW
X
Bit 6
RW
X
Bit 5
RW
X
Bit 4
RW
X
Bit 3
RW
X
Bit 2
RW
X
Bit 1
RW
X
Bit 0
RW
X
SMBus Table: Vendor & Revision ID Register
Pin #
Name
Control Function Type0
1PWD
Bit 7
RID3
R
-
0
Bit 6
RID2
R
-
0
Bit 5
RID1
R
-
0
Bit 4
RID0
R
-
1
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
RESERVED
-
RESERVED
-
VENDOR ID
-
Byte 3
-
REVISION ID
-
Byte 2
RESERVED
-
Byte 1
-
RESERVED
-
RESERVED
-
RESERVED
-
Byte 0
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
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