參數(shù)資料
型號: 95V857AKILF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
封裝: LEAD FREE, MLF-40
文件頁數(shù): 10/13頁
文件大?。?/td> 128K
代理商: 95V857AKILF-T
6
ICS95V857I
0820A—08/02/04
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
TA = -40 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.5V+0.2V @ 25
oC
45
233
MHz
Application Frequency
Range
freqApp
2.5V+0.2V @ 25
oC
95
210
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
15
s
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
tPLL
1
CLK_IN to any output
5.5
ns
Output enable time
tEN
PD# to any output
5
ns
Output disable time
tdis
PD# to any output
5
ns
Period jitter
Tjit (per)
100MHz to 200MHz
-30
30
ps
Half-period jitter
t(jit_hper)
100MHz to 200MHz
-75
30
ps
Input clock slew rate
tsl(i)
14
V/ns
Output clock slew rate
tsl(o)
12.5
V/ns
Cycle to Cycle Jitter
1
Tcyc-Tcyc
100MHz to 200MHz
60
ps
Phase error
t(phase error)
4
-50
0
50
ps
Output to Output Skew
Tskew
60
ps
相關(guān)PDF資料
PDF描述
95V857AGI-T PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
95V857AGT 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
95V857AKT-LF 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40
95V857ALLF-T 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
95V857AGLF-T 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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