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參數(shù)資料
| 型號： | 95V847AGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 95V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.173 INCH, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 145K |
| 代理商： | 95V847AGLFT |
2
ICS95V847
0718D—04/08/05
Pin Descriptions
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
ICS95V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential
pair of clock outputs (CLKT[4:0], CLKC[4:0]) and one differential pair feedback clock output (FB_OUT, FB_OUTC).The
clock outputs are controlled by input clock (CLK_INT, CLK_INC), the feedback clock (FB_INT, FB_INC) and the analog
power input (AVDD). When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in ICS95V847 clock driver uses the input clock (CLK_INC, CLK_INT) and the feedback clock (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter differential output clocks (CLKT[4:0], CLKC[4:0]). ICS95V847
is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS95V847 is characterized for operation from 0°C to 85°C.
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