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| 型號(hào)： | 95V157YG-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 0.240 INCH, MO-153, TSSOP-48 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 209K |
| 代理商： | 95V157YG-T |
4
ICS95V157
0501C—11/24/08
Recommended Operating Condition (see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDD, AVDD
2.3
2.5
2.7
V
CLK_INT, FB_INT
0.4
VDD/2 - 0.18
V
PD#
-0.3
0.7
V
CLK_INT, FB_INT
VDD/2 + 0.18
2.1
V
PD#
1.7
VDD + 0.6
V
DC input signal voltage
(note 2)
VIN
-0.3
VDD + 0.3
V
Output differential cross-
voltage (note 4)
VOX
VDD/2 - 0.15
VDD/2 + 0.15
V
High level output
current
IOH
-6.4
mA
Low level output current
IOL
5.5
mA
Operating free-air
temperature
TA
085
°C
Low level input voltage
VIL
High level input voltage
VIH
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3.
Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4.
Differential cross-point voltage is expected to track variations of VDD and is the
voltage at which the differential signal must be crossing.
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