參數(shù)資料
型號(hào)： 954206BFLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, M0-118N, SSOP-56
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 315K
代理商： 954206BFLFT
8
Integrated
Circuit
Systems, Inc.
ICS954206B
Advance Information
0940—06/23/05
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
NOTES
Current Source Output Impedance
Zo
VO = Vx
3000
1
Voltage High
VHigh
660
850
mV
1,3
Voltage Low
VLow
-150
150
mV
1,3
Max Voltage
Vovs
1150
mV
1
Min Voltage
Vuds
-300
mV
1
Crossing Voltage (abs)
Vx(abs)
250
550
mV
1
Crossing Voltage (var)
d-Vx
Variation of crossing over all
edges
140
mV
1
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
400MHz nominal
2.4993
2.5008
ns
2
400MHz spread
2.4993
2.5133
ns
2
333.33MHz nominal
2.9991
3.0009
ns
2
333.33MHz spread
2.9991
3.016
ns
2
266.66MHz nominal
3.7489
3.7511
ns
2
266.66MHz spread
3.7489
3.77
ns
2
200MHz nominal
4.9985
5.0015
ns
2
200MHz spread
4.9985
5.0266
ns
2
166.66MHz nominal
5.9982
6.0018
ns
2
166.66MHz spread
5.9982
6.0320
ns
2
133.33MHz nominal
7.4978
7.5023
ns
2
133.33MHz spread
7.4978
7.5400
ns
2
100.00MHz nominal
9.9970
10.0030
ns
2
100.00MHz spread
9.9970
10.0533
ns
2
400MHz nominal/spread
2.4143
ns
1,2
333.33MHz nominal/spread
2.9141
ns
1,2
266.66MHz nominal/spread
3.6639
ns
1,2
200MHz nominal/spread
4.8735
ns
1,2
166.66MHz nominal/spread
5.8732
ns
1,2
133.33MHz nominal/spread
7.3728
ns
1,2
100.00MHz nominal/spread
9.8720
ns
1,2
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
VOL = 0.175V, VOH = 0.525V
125
ps
1
Fall Time Variation
d-tf
VOH = 0.525V VOL = 0.175V
125
ps
1
Duty Cycle
dt3
Measurement from differential
wavefrom
45
55
%
1
Skew
tsk3
CPU(1:0), VT = 50%
100
ps
1
Skew
tsk4
CPU(1:0) to CPU2_ITP,
VT = 50%
150
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
Measurement from differential
wavefrom (CPU2_ITP)
125
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
Measurement from differential
wavefrom, (CPU(1:0))
85
ps
1
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, ΙREF = 475
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3I
REF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
Statistical measurement on single
ended signal
Measurement on single ended
signal using absolute value.
Average period
Tperiod
Absolute min period
Tabsmin
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