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參數(shù)資料
| 型號(hào)： | 953002DFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁(yè)數(shù)： | 12/35頁(yè) |
| 文件大?。?/td> | 280K |
| 代理商： | 953002DFLF |
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2
Integrated
Circuit
Systems, Inc.
ICS953002
0924—11/18/09
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
VDDA
PWR
3.3V power for the PLL core.
2
GND
PWR
Ground pin.
3
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
4
**FSL0/REF0
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 14.318 MHz reference
5
FSL1/REF1
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 14.318 MHz reference
6
X1
IN
Crystal input, Nominally 14.318MHz.
7
X2
OUT
Crystal output, Nominally 14.318MHz
8
GNDREF
PWR
Ground pin for the REF outputs.
9
VttPWR_GD/PD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active high
input. / Asynchronous active low input pin used to power down the device
into a low power state.
10
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
11
**FSL2/PCICLK0
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 3.3V PCI clock output.
12
**FS3/~PCICLK1
I/O
Frequency select latch input pin / 3.3V PCI clock output.
13
PCICLK2
OUT
PCI clock output.
14
PCICLK3
OUT
PCI clock output.
15
GNDPCI
PWR
Ground pin for the PCI outputs
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
PCICLK4
OUT
PCI clock output.
18
PCICLK5
OUT
PCI clock output.
19
GNDPCI
PWR
Ground pin for the PCI outputs
20
*Turbo#
IN
Real time input pin to change frequency to a pre-programmed under or over
clock entries located in the Rom table.
21
Reset#
OUT
Real time system reset signal for frequency gear ratio change or watchdog
timer timeout. This signal is active low.
22
VDD48
PWR
Power pin for the 48MHz output.3.3V
23
**Mode0/48MHz
I/O
Function select pin, 1=Mobile Mode, 0=Desktop Mode / 48MHz clock output.
3.3V.
24
*Sel24_48#/24_48MHz
I/O
Latched select input for 24/48MHz output / 24/48MHz clock output.
1=24MHz, 0 = 48MHz.
25
GND48
PWR
Ground pin for the 48MHz outputs
26
VDD3V66
PWR
Power pin for the 3.3V 66MHz clocks.
27
**ITP_EN/3V66_2
I/O
3.3V 66.66MHz clock output./
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
0 = PCI-EX0 pair
28
**FS4/3V66_1
I/O
Frequency select latch input pin / 66.66MHz clock output. 3.3V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 953002DFLFT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 953004-1 | 制造商:TE Connectivity 功能描述:SOCKET HEADER 32WAY 制造商:TE Connectivity 功能描述:SOCKET, HEADER, 32WAY 制造商:TE Connectivity 功能描述:SOCKET, HEADER, 32WAY; Connector Type:Wire to Board; Contact Termination:Through Hole Right Angle; Gender:Receptacle; No. of Contacts:32; No. of Rows:2; Pitch Spacing:2.54mm; Contact Plating:Tin; Contact Material:Bronz ;RoHS Compliant: Yes |
| 953-004-1-100-2 | 制造商:3M Electronic Products Division 功能描述: |
| 953008BFLF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 953008BFLFT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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