參數(shù)資料
型號: 950810YGLF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, LEAD FREE, MO-153, TSSOP-56
文件頁數(shù): 3/19頁
文件大?。?/td> 202K
代理商: 950810YGLF-T
11
ICS950810
0472F—01/12/04
I2C Tables
Pin #
Name
0
1
PWD
Bit 7
-
Spread Enabled
Spread Spectrum Control
RW
OFF
ON
0
Bit 6
-
CPU_T(2:0)
Power down mode output
level
0= CPU driven in power
down
1= undriven
RW
HIGH
LOW
0
Bit 5
35
3V66_1/VCH_CLK
VCH/66.66 Select
RW
66.66
48.00
0
Bit 4
53
CPU_STOP#*
Reflects value of pin
R
Stop
Active
X
Bit 3
34
PCI_STOP#*
Reflects value of pin at
power up. Also can be set.
R/RW
Stop
Active
1
Bit 2
40
FS2
Frequency Selection
RW
-
X
Bit 1
55
FS1
Frequency Selection
RW
-
X
Bit 0
54
FS0
Frequency Selection
RW
-
X
Control Function
Affected Pin
BYTE
0Type
Bit Control
Pin #
Name
0
1
PWD
Bit 7
43
MULTSEL0*
Reflects value of pin
R
-
x
Bit 6
-
CPU_T(2:0)
CPU_Stop mode output level
0= CPU driven when stopped
1 = undriven
RW
HIGH
LOW
0
Bit 5
45, 44
CPUCLKT2
CPUCLKC2
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
0
Bit 4
49, 48
CPUCLKT1
CPUCLKC1
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
0
Bit 3
52, 51
CPUCLKT0
CPUCLKC0
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
0
Bit 2
45, 44
CPUCLKT2
CPUCLKC2
Output control
RW
Disable Enable
1
Bit 1
49, 48
CPUCLKT1
CPUCLKC1
Output control
RW
Disable Enable
1
Bit 0
52, 51
CPUCLKT2
CPUCLKC2
Output control
RW
Disable Enable
1
BYTE
1
Control Function
Affected Pin
Type
Bit Control
相關(guān)PDF資料
PDF描述
950810YFLF-T 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
950810YG-T 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
08056C103JA79A Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:30; Connector Shell Size:32; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle; Body Style:Straight
950811YGT 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
950811YGLFT 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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