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參數(shù)資料
| 型號： | 950218AFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 331K |
| 代理商： | 950218AFLFT |
16
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950218
Preliminary Product Preview
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming
resistors should be located close to the series termination
resistor to minimize the current loop area. It is more important
to locate the series termination resistor close to the driver
than the programming resistor.
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| 08053C103MA72A | General Specifications |
| 950218AFLF | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 08053C103MA74A | General Specifications |
| 95022-T43 | MODULAR TERMINAL BLOCK |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 95022 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CHUCK |
| 95022 NC003 | 制造商:Alpha Wire Company 功能描述:BRAID BARE COPP FLAT NO CLR 250' |
| 95022 NC199 | 制造商:Alpha Wire Company 功能描述:BRAID BARE COPPER FLAT 100=100' |
| 950220AFLF | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Dual 48-Pin SSOP Tube |
| 950220AFLFT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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