- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24862 > 950201YGLF-T (INTEGRATED DEVICE TECHNOLOGY INC) PROC SPECIFIC CLOCK GENERATOR, PDSO56 PDF資料下載
參數(shù)資料
| 型號(hào)： | 950201YGLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁(yè)數(shù)： | 12/15頁(yè) |
| 文件大?。?/td> | 204K |
| 代理商： | 950201YGLF-T |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)
IDTTM Programmable Timing Control HubTM for P4TM
460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
6
Byte 0: Control Register
Byte 1: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via I
2C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I
2C Byte 0 Bit3. In Software mode it is not allowed to pull the external
PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions.
The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these
modes.
In Hardware mode the I
2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
2C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC
off, and external resistor termination will bring CPUCLKC low.
t
i
B#
n
i
Pe
m
a
ND
W
P
2
e
p
y
T
1
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B4
50
S
FX
R
n
o
d
e
l
p
m
a
s
n
i
p
0
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
1
t
i
B5
51
S
FX
R
n
o
d
e
l
p
m
a
s
n
i
p
1
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
2
t
i
B0
42
S
FX
R
n
o
d
e
l
p
m
a
s
n
i
p
2
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
3
t
i
B4
3#
P
O
T
S
_
I
C
P
3
XR
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
:
e
d
o
m
e
r
a
w
d
r
a
H
D
W
P
n
o
d
e
l
p
m
a
s
n
i
p
#
P
O
T
S
_
I
C
P
1W
R
:
e
d
o
m
e
r
a
w
t
f
o
S
d
e
p
o
t
s
K
L
C
I
C
P
=
0
d
e
p
o
t
s
t
o
n
K
L
C
I
C
P
=
1
4
t
i
B3
5#
P
O
T
S
_
U
P
CX
R
l
a
n
r
e
t
x
e
h
t
f
o
e
u
l
a
v
t
n
e
r
u
c
e
h
t
s
t
c
e
l
f
e
R
n
i
p
#
P
O
T
S
_
U
P
C
5
t
i
B5
3H
C
V
/
1
_
6
V
30
W
R
z
H
M
8
4
/
z
H
M
6
t
c
e
l
e
S
H
C
V
z
H
M
8
4
=
1
,
z
H
M
6
=
0
6
t
i
B-
0
)
d
e
v
r
e
s
e
R
(
7
t
i
B-
d
a
e
r
p
S
d
e
l
b
a
n
E
0W
Rn
O
d
a
e
r
p
S
=
1
,
f
O
d
a
e
r
p
S
=
0
t
i
B#
n
i
Pe
m
a
ND
W
P
2
e
p
y
T
1
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B1
5
,
2
5
0
T
K
L
C
U
P
C
0
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
1
t
i
B8
4
,
9
4
1
T
K
L
C
U
P
C
1
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
2
t
i
B4
4
,
5
4
2
T
K
L
C
U
P
C
2
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
3
t
i
B1
5
,
2
5
0
T
K
L
C
U
P
C
0
C
K
L
C
U
P
C
0W
R
n
o
i
t
r
e
s
a
h
t
i
w
0
C
/
0
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
r
F
=
1
g
n
i
n
u
r
e
r
f
t
o
N
=
0
#
P
O
T
S
_
U
P
C
f
o
g
n
i
n
u
r
4
t
i
B8
4
,
9
4
1
T
K
L
C
U
P
C
1
C
K
L
C
U
P
C
0W
R
n
o
i
t
r
e
s
a
h
t
i
w
1
C
/
1
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
r
F
=
1
g
n
i
n
u
r
e
r
f
t
o
N
=
0
#
P
O
T
S
_
U
P
C
f
o
g
n
i
n
u
r
5
t
i
B4
4
,
5
4
2
T
K
L
C
U
P
C
2
C
K
L
C
U
P
C
0W
R
n
o
i
t
r
e
s
a
h
t
i
w
2
C
/
2
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
r
F
=
1
g
n
i
n
u
r
e
r
f
t
o
N
=
0
#
P
O
T
S
_
U
P
C
f
o
g
n
i
n
u
r
6
t
i
B-
-
0
-
)
d
e
v
r
e
s
e
R
(
7
t
i
B3
40
L
E
S
T
L
U
MX
R
0
L
E
S
T
L
U
M
f
o
e
u
l
a
v
t
n
e
r
u
c
e
h
t
s
t
c
e
l
f
e
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 950211BFL-T | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 950211BFLF | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 08053C103KA72A | General Specifications |
| 950211BFLFT | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 950211BFT | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 950-202 | 制造商:Mitutoyo Corporation 功能描述:Wire Gage American Std Wire Gage; American Standard Wire Gage ;RoHS Compliant: NA |
| 950-202001E | 制造商:Vero 功能描述:Bulk 制造商:VERO 功能描述:TAPPED STRIP 制造商:Vero Technologies 功能描述:TAPPED STRIP 制造商:Vero Technologies 功能描述:POWER STRIP OUTLET; Accessory Type:Tapped Strip; For Use With:Subracks; Body Material:Steel; External Width:16.7" ;RoHS Compliant: Yes |
| 950-202589L | 制造商:VERO 功能描述:SUBRACK 3U 84HP 240MM |
| 950-202594G | 制造商:VERO 功能描述:SUBRACK 3U 84HP 360MM |
| 950-202594G | 制造商:VERO 功能描述:SUBRACK 3U 84HP 360MM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。