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參數(shù)資料
| 型號： | 94227AF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, MO-118, SSOP-48 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 151K |
| 代理商： | 94227AF |
6
ICS94227
0446B—12/20/02
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B
0
2
18
K
L
C
I
C
P
6
t
i
B
8
1
17
K
L
C
I
C
P
5
t
i
B
7
1
16
K
L
C
I
C
P
4
t
i
B
6
1
15
K
L
C
I
C
P
3
t
i
B
4
1
14
K
L
C
I
C
P
2
t
i
B
3
1
13
K
L
C
I
C
P
1
t
i
B
1
12
K
L
C
I
C
P
0
t
i
B
0
1
11
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
#
1
S
F
6
t
i
B-
1
#
0
S
F
5
t
i
B4
41
1
C
I
P
A
O
I
4
t
i
B5
41
0
C
I
P
A
O
I
3
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B7
41
1
F
E
R
0
t
i
B8
41
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-X
#
2
S
F
6
t
i
B
-
0
8
4
_
4
2
L
E
S
z
H
M
8
4
=
1
z
H
M
4
2
=
0
5
t
i
B
6
1z
H
M
8
4
t
i
B
7
1z
H
M
8
4
_
4
2
3
t
i
B
9
10
K
L
C
I
C
P
2
t
i
B
7
2
12
K
L
C
P
G
A
1
t
i
B
6
2
11
K
L
C
P
G
A
0
t
i
B
3
2
10
K
L
C
P
G
A
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don’t write into this register, writing into this
register can cause malfunction
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B5
30
;
#
F
U
P
C
_
L
E
S
g
n
i
n
u
r
e
r
f
e
b
l
i
w
2
K
L
C
U
P
C
=
0
g
n
i
n
u
r
e
r
f
e
b
t
o
n
l
i
w
2
K
L
C
U
P
C
=
1
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
X
#
4
S
F
4
t
i
B-
X
#
3
S
F
3
t
i
B5
31
2
K
L
C
U
P
C
2
t
i
B8
31
1
K
L
C
U
P
C
1
t
i
B9
31
0
K
L
C
U
P
C
0
t
i
B2
41
2
C
I
P
A
O
I
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
d
e
v
r
e
s
e
R
(
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
X
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
X
)
d
e
v
r
e
s
e
R
(
3
t
i
B-
X
)
d
e
v
r
e
s
e
R
(
2
t
i
B-
X
)
d
e
v
r
e
s
e
R
(
1
t
i
B-
X
)
d
e
v
r
e
s
e
R
(
0
t
i
B-
X
)
d
e
v
r
e
s
e
R
(
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PDF描述 |
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