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參數(shù)資料
| 型號： | 94211AFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 157K |
| 代理商： | 94211AFLFT |
10
ICS94211
0441E—11/17/04
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
CL = max cap loads;
CPU=66-133 MHz, SDRAM=100 MHz
124
350
CPU=133 MHz, SDRAM=133 MHz
135
500
IDD2.5OP
CL = max cap loads;
18
70
Powerdown Current
IDD3.3PD
CL = 0 pF; Input address to VDD or GND
600
mA
Input Frequency
Fi
VDD = 3.3 V
14.318
MHz
Pin Inductance
Lpin
7nH
CIN
Logic Inputs
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
27
45
pF
Transition time
1
Ttrans
To 1st crossing of target frequency
3
ms
Settling time
1
Ts
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target frequency
3
ms
tPZH,tPZL
Output enable delay (all outputs)
1
10
ns
tPHZ,tPLZ
Output disable delay (all outputs)
1
10
ns
Skew
1
tcpu-pci VT = 1.5V; VTL=1.25V
2.45
4
ns
1Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
Input Low Current
mA
IDD3.3OP
Operating Supply
Current
mA
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