參數(shù)資料
型號: 94211AFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, GREEN, MO-118, SSOP-48
文件頁數(shù): 7/18頁
文件大?。?/td> 157K
代理商: 94211AFLF
15
ICS94211
0441E—11/17/04
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94211. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94211 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94211 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94211.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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