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參數(shù)資料
| 型號： | 93718CFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 93718 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 12 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 96K |
| 代理商： | 93718CFLF |
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
DDR_Mode (SEL_DDR = 1), VDD = 2.5±5%
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Operating Frequency
66
133
200
MHz
Input clock duty cycle
dtin
40
50
60
%
Output to Output Skew
Tskew
Output crossover skew DDR[0:11]
80
100
ps
66MHz to 100MHz, w/loads
48
49
52
%
101MHz to 167MHz, w/loads
47
50
53
%
Rise Time, Fall Time (DDR
Outputs)
trd, tfd
Measured between 20% and 80%
output, w/loads
500
600
700
ps
Duty cycle
DC
2
Switching Characteristics
SD_Mode (SEL_DDR = 0), VDD = 3.3±5%
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Operating Frequency
66
133
200
MHz
Input clock duty cycle
dtin
40
50
60
%
Output to Output Skew
Tskew
VT = 1.50V
150
ps
Duty cycle
DC
2
66MHz to 200MHz
54
%
Rise Time, Fall Time
(SDRAM Outputs)
trs, tfs
VOL = 0.4V, VOH = 2.4V, w/loads
0.5
1.5
1.7
ns
SDRAM Buffer LH Prop.
Delay
1
t
PLH
Input edge greater than 1V/ns
2
2.5
ns
SDRAM Bufer HL Prop.
Delay
1
t
PHL
Input edge greater than 1V/ns
1.9
2.5
ns
Notes:
1. Refers to transition on non-inverting output.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=t2/t1, were the cycle (t1) decreases
as the frequency goes up.
Switching Characteristics
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