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參數(shù)資料
| 型號(hào)： | 935273871551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 23/61頁 |
| 文件大小： | 326K |
| 代理商： | 935273871551 |
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2004 May 18
3
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
1
FEATURES
3.3 V power supply
Triple 8-bit ADC:
– 0.25 LSB differential non-linearity (DNL)
– 0.6 LSB integral non-linearity (INL).
Analog sampling rate from 12 Msps up to 270 Msps
Maximum data rate:
– Single port mode: 140 MHz
– Dual port mode: 270 MHz
– 3.3 V LV-TTL outputs.
PLL control via I2C-bus:
– 390 ps PLL jitter peak to peak at 270 MHz
– Low PLL drift with temperature (2 phase steps
maximum)
– PLL generates the ADC sampling clock which can be
locked on the line frequency from 15 kHz to 150 kHz
– Integrated PLL divider
– Programmable phase clock adjustment cells.
Three clamp circuits for programming a clamp code
from
24 to +136 by steps of 1 LSB (mid-scale clamping
for YUV signal)
Internal generation of clamp signal
Three independent blanking functions
Input:
– 700 MHz analog bandwidth
– Two independent analog inputs selectable via
I2C-bus
– Analog input from 0.5 V to 1 V (p-p) to produce a
full-scale ADC input of 1 V (p-p)
– Three controllable amplifiers: gain control via I2C-bus
to produce full-scale peak-to-peak output with a half
LSB resolution.
Synchronisation:
– Frame and field detection for interlaced video signal
– Parasite synchronization pulse detection and
suppression
– Sync processing for composite sync, 3-level sync and
sync-on-green signals
– Polarity and activity detection.
IC control via I2C-bus serial interface
Power-down mode
LQFP144 and LBGA208 package:
– LBGA208 package pin to pin compatible with
TDA8756.
2
APPLICATIONS
RGB/YUV high-speed digitizing
LCD panels drive
LCD projection system
New TV concept.
3
GENERAL DESCRIPTION
The TDA8754 is a complete triple 8-bit ADC with an
integrated PLL running up to 270 Msps and analog
preprocessing functions (clamp and PGA) optimized for
capturing RGB/YUV graphic signals.
The PLL generates a pixel clock from inputs HSYNC and
COAST.
The TDA8754 offers full sync processing for
sync-on-green applications. A clamp signal may be
generated internally or provided externally.
The clamp levels, gains and other settings are controlled
via the I2C-bus interface.
This IC supports display resolutions up to QXGA
(2048
× 1536) at 85 Hz.
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