參數(shù)資料
型號： 935272703551
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144
文件頁數(shù)： 9/61頁
文件大?。?/td> 326K
代理商： 935272703551
2004 May 18
17
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
8.2.4
CLAMP
Three independent parallel clamping circuits are used to
clamp the video input signals on programmable black
levels. The clamp levels may be set from
24 to +136 LSBs in steps of 1 LSB. They are controlled
by three 9-bit I2C-bus registers (OFFSETR, OFFSETG
and OFFSETB).
The clamp pulse can be generated internally (based on the
PLL clock reference) or can be externally applied on
pin CLP.
By setting correctly the I2C-bus bits, it is possible to inhibit
the clamp request with the Vsync signal. This inhibition will
be effected by forcing logic 0 on the clamp request output.
It should be noted that the clamp period can start on the
falling edge of the clamp request and that the high level of
the clamp request sets the ADC outputs in the blanking
mode. This means that by forcing the clamp signal request
to logic 0 by using Vsync, a falling edge may happen on
the clamp request if this signal was at logic 1 before
enforcing the inhibition. To avoid this, the user has to
guarantee that the Vsync signal used for the clamp
inhibition will not be set during a high level of the clamp
request signal.
Remark: If signal Vsync is coming from the external
pin VSYNC, this signal may be used to coast the PLL.
In order to properly do the coast, the edge of signal Vsync
(COAST) must not appear at the same time as the edge of
signal Hsync. This condition is similar to the pin CLP
inhibition condition.
8.2.5
AGC
Three independent variable gain amplifiers are used to
provide, for each channel, a full-scale input signal to the
8-bit ADC. The gain adjustment range is designed in such
a way that for an input range varying from 0.5 to 1 V (p-p),
the output signal corresponds to the ADC full-scale input
of 1 V (p-p).
8.3
HSOSEL, DEO and SCHCKREFO
Bit HSOSEL allows to have a full correlation phase
behaviour between outputs CKDATA and HSYNCO when
bit HSOSEL = 0 (Hsync from counter). If HSOSEL = 0 and
bits PA4 to PA0 of register PHASE are changed to chose
the best sampling time, the phase relationship between
outputs CKDATA and HSYNCO will stay unchanged. After
the video standard is determined, bit HSOSEL must be set
to a logic 0 for normal operation mode.
To use the Hsync from the counter the registers HSYNCL,
HBACKL, HDISPLMSB and HDISPLLSB should be set
properly in order to create the correct HSYNCO and DEO
output signals (see Figs.5 and 6), which is depending on
video standard. Output signal DEO should be used to
determine the first active pixel.
The demultiplexed mode should be used (bit DMX = 1)
and the output flow is alternated between port A and port B
in case the sampling frequency is over 140 Msps (clock
frequency). It is necessary, in order to warrant that the
outputs HSYNCO and DEO are always changing on
CKDATA output rising edge (see Fig.7), that the values
HSYNCL, HBACKL and HDISPL (see Fig.5) are even
value. If an odd value is entered the outputs HSYNCO and
DEO can change state during falling edge, which is not
compliant with the th(o) and td(o) specified output timing.
Bit SCHCKREFO is used if in demultiplexed mode one
pixel shift is needed in the DEO signal (to move the screen
one vertical line). By setting bit SCHCKREFO from a
logic 0 to a logic 1 a left move is obtained, also the timing
relationship between HSYNCO, DEO and CKDATA stays
unchanged. An even number of pixel moves is done by
changing the value of HBACKL and HSYNCL. The correct
combination of bits HBACKL, HSYNCL and SCHCKREFO
places the first active pixel at the beginning of the screen
with always the correct phase relationship between
outputs DEO, HSYNCO and CKDATA.
Bit HSOSEL should be set to a logic 0 only after the PLL is
stable, so only after the video standard has been found
and correct PLL parameters have been set in the
TDA8754. Bit HSOSEL should be set to a logic 1 to have
a stable HSYNCO signal during the video recognition. The
video standard can be recognized by using the signals
FIELDO, VSYNCO and HSYNCO. The phase relation
between CKDATA and HSYNCO (or DEO) is undefined if
bit HSOSEL = 1.
8.4
PLL
The ADCs are clocked by either the internal PLL locked to
the reference clock (Hsync from input or Hsync from sync
separator) or to an external clock connected to
pin CKEXT. This selection is performed via the I2C-bus by
setting bit CKEXT. To use the external clock, bit CKEXT
must be reset to logic 1.
The PLL phase frequency detector can be disconnected
during the frame flyback (vertical blanking) or the
unavailability of the Ckref signal by using the coast
function. The coast signal can be derived from the
VSYNC1(2) input, from the Vsync extracted by the sync
separator or from the coast input. The coast function can
be disabled with bit COE.
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