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參數(shù)資料
| 型號： | 935272034125 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5 |
| 封裝： | PLASTIC, SC-74A, SOT-753, 5 PIN |
| 文件頁數(shù)： | 12/27頁 |
| 文件大?。?/td> | 179K |
| 代理商： | 935272034125 |
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2002 Nov 15
2
Philips Semiconductors
Product specication
Bilateral switch
74LVC1G66
FEATURES
Very low ON resistance:
– 7.5
(typical) at VCC = 2.7 V
– 6.5
(typical) at VCC = 3.3 V
–6
(typical) at VCC =5V.
High noise immunity
CMOS low power consumption
Latch up performance exceeds 250 mA
Direct interface TTL-levels
Multiple package options
ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +125 °C.
DESCRIPTION
The 74LVC1G66 is a high-speed Si-gate CMOS device.
The 74LVC1G66 provides an analog switch. The switch
has two input/output pins (Y and Z) and an active HIGH
enable input pin (E). When pin E is LOW, the analog
switch is turned off.
QUICK REFERENCE DATA
Ground = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPZH/tPZL
turn-on time E to VOS
CL = 50 pF; RL = 500 ; VCC = 3 V
2.5
ns
CL = 50 pF; RL = 500 ; VCC = 5 V
1.9
ns
tPHZ/tPLZ
turn-off time E to VOS
CL = 50 pF; RL = 500 ; VCC = 3 V
3.4
ns
CL = 50 pF; RL = 500 ; VCC = 5 V
2.5
ns
CI
input capacitance
2
pF
CPD
power dissipation capacitance
CL = 50 pF; f = 10 MHz; VCC = 3.3 V;
notes 1 and 2
16
pF
CS
switch capacitance
OFF-state
5
pF
ON-state
9.5
pF
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