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參數(shù)資料
| 型號(hào)： | 935272029125 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | LVC/LCX/Z SERIES, 1-INPUT NON-INVERT GATE, PDSO5 |
| 封裝： | PLASTIC, SOT-753, SC-74A, 5 PIN |
| 文件頁數(shù)： | 9/19頁 |
| 文件大小： | 137K |
| 代理商： | 935272029125 |
Philips Semiconductors - PIP - 74LVC1G07; Buffer with open-drain output
Product Information
74LVC1G07; Buffer
with open-drain
output
Information as of 2003-04-22
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Download datasheet
Block diagram
topGeneral description
The 74LVC1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families.
The input can be driven from either 3.3 or 5 V devices. This feature allows the use of this device as translator in a
mixed 3.3 and 5 V environment.
Schmitt trigger action at the input makes the circuit tolerant for slower input rise and fall time.
The 74LVC1G07 provides the non-inverting buffer.
The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW
wired-OR or active-HIGH wired-AND functions.
topFeatures
q
Wide supply voltage range from 1.65 to 5.5 V
q
High noise immunity
q
Complies with JEDEC standard:
r
JESD8-7 (1.65 to 1.95 V)
r
JESD8-5 (2.3 to 2.7 V)
r
JESD8B/JESD36 (2.7 to 3.6 V).
q
24 mA output drive (VCC = 3.0 V)
q
CMOS low power consumption
q
Latch-up performance exceeds 250 mA
q
Direct interface with TTL levels
q
Inputs accept voltages up to 5 V
q
Multiple package options
q
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
q
Specified from -40 to +85 Cel and -40 to +125 Cel.
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LVC1G07GW.html (1 of 3) [May-12-2003 2:34:22 PM]
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