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參數(shù)資料
| 型號： | 935272020125 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO5 |
| 封裝： | PLASTIC, SOT-353, 5 PIN |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 69K |
| 代理商： | 935272020125 |
2001 Apr 04
2
Philips Semiconductors
Product specication
Single D-type ip-op; positive-edge trigger
74LVC1G79
FEATURES
Wide supply voltage range from 1.65 to 5.5 V
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance ≤250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
SOT353 package.
DESCRIPTION
The 74LVC1G79 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of this device in a mixed 3.3 and 5 V
environment.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G79 provides a single positive-edge triggered
D-type flip-flop.
Information on the data input is transferred to the Q output
on the LOW-to-HIGH transition of the clock pulse.
The D input must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Note
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi +(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay CP to Q
VCC = 1.8 V; CL = 30 pF; RL =1k
3.6
ns
VCC = 2.5 V; CL = 30 pF; RL = 500
2.3
ns
VCC = 3.3 V; CL = 50 pF; RL = 500
2.2
ns
VCC = 5.0 V; CL = 50 pF; RL = 500
1.7
ns
CI
input capacitance
5
pF
CPD
power dissipation capacitance per
buffer
VCC = 3.3 V; note 1
17
pF
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