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參數(shù)資料
| 型號： | 935272002118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PQCC20 |
| 封裝： | 5 X 5 MM, 0.85 MM HEIGHT, HEAT SINK, PLASTIC, MO-220, SOT-662-1, VQFN-20 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 137K |
| 代理商： | 935272002118 |
Philips Semiconductors
Product data
PCA9544
4-channel I2C multiplexer with interrupt logic
2002 Jul 26
8
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
SW00368
DATA OUTPUT
BY RECEIVER
12
89
S
START condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
Figure 10. Acknowledgement on the I2C-bus
SDA
S0
A
1
0
A2
A1
A0
SLAVE ADDRESS
start condition
R/W
acknowledge
from slave
acknowledge
from slave
B0
CONTROL REGISTER
P
SW00802
B1
B2
X
XX
X
Figure 11. WRITE control register
SDA
S1
A
NA
1
0
A2
A1
A0
start condition
R/W
acknowledge
from slave
CONTROL REGISTER
P
stop condition
last byte
SW00378
SLAVE ADDRESS
no acknowledge
from master
B0
INT0
B1
INT1
B2
INT2
X
INT3
Figure 12. READ control register
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