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參數(shù)資料
| 型號： | 935271265557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 108K |
| 代理商： | 935271265557 |
Philips Semiconductors
Product data
SSTV16859
2.5 V 13-bit to 26-bit SSTL_2
registered buffer for stacked DDR DIMM
2002 Feb 19
10
AC WAVEFORMS
SW00752
VDD/2
LVCMOS
RESET
10%
IDD
tinact
VDD
VDD/2
tact
90%
Waveform 1. Inputs active and inactive times (see Note 1)
VREF
VIH
VIL
INPUT
SW00753
tW
Waveform 2. Pulse duration
SW00754
VICR
VI(PP)
TIMING
INPUT
OUTPUT
tPLH
tPHL
VTT
VOH
VOL
Waveform 3. Propagation delay times
Input
SW00755
VIH
LVCMOS RESET
VDD/2
VIL
VOH
VOL
VTT
tPHL
Output
Waveform 4. Propagation delay times
VICR
VI(PP)
Timing input
SW00756
VREF
VIL
Input
th
tsu
VIH
Waveform 5. Setup and hold times
NOTES:
1. IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
2. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , input slew rate = 1 V/ns ± 20%
(unless otherwise specified).
3. The outputs are measured one at a time with one transition per measurement.
4. VTT = VREF = VDD/2
5. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
6. VIL = VREF – 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
7. tPLH and tPHL are the same as tpd.
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