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參數(shù)資料
| 型號： | 935271208112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 105K |
| 代理商： | 935271208112 |
Philips Semiconductors
Product data
PCA9546
4-channel I2C switch with reset
2
2002 Feb 19
853-2317 27757
FEATURES
1-of-4 bi-directional translating switches
I2C interface logic; compatible with SMBus standards
Active Low Reset Input
3 address pins allowing up to 8 devices on the I2C bus
Channel selection via I2C bus, in any combination
Power up with all switch channels deselected
Low Rds
ON switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
No glitch on power-up
Supports hot insertion
Low stand-by current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant Inputs
0 to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Package Offer: SO16, TSSOP16
DESCRIPTION
The PCA9546 is a quad bi-directional translating switch controlled
by the I2C bus. The SCL/SDA upstream pair fans out to four
downstream pairs, or channels. Any individual SCx/SDx channel or
combination of channels can be selected, determined by the
contents of the programmable Control Register.
An active-LOW reset input allows the PCA9546 to recover from a
situation where one of the downstream I2C buses is stuck in a LOW
state. Pulling the RESET pin LOW resets the I2C state machine and
causes all the channels to be deselected as does the internal power
on reset function.
The pass gates of the switches are constructed such that the VDD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9546. This allows the use of different bus
voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SW00913
A0
A1
RESET
SD0
SC0
SD1
SC1
VSS
VDD
SDA
SCL
A2
SC3
SD3
SC2
SD2
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
A0
Address input 0
2
A1
Address input 1
3
RESET
Active LOW reset input
4
SD0
Serial data 0
5
SC0
Serial clock 0
6
SD1
Serial data 1
7
SC1
Serial clock 1
8
VSS
Supply ground
9
SD2
Serial data 2
10
SC2
Serial clock 2
11
SD3
Serial data 3
12
SC3
Serial clock 3
13
A2
Address input 2
14
SCL
Serial clock line
15
SDA
Serial data line
16
VDD
Supply voltage
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
16-Pin Plastic SO
–40 to +85
°C
PCA9546D
SOT109-1
16-Pin Plastic TSSOP
–40 to +85
°C
PCA9546PW
SOT403-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
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