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參數(shù)資料
| 型號(hào)： | 935270986115 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| 封裝： | 1.50 MM, PLASTIC, SOT-23, SOT-25, SO-5 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大小： | 174K |
| 代理商： | 935270986115 |
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Philips Semiconductors
Product data
NE56632-XX
Active-LOW system reset with adjustable delay time
2002 Mar 25
10
TIMING DIAGRAM
The timing diagram in Figure 23 depicts the operation of the device.
Letters A–N on the TIME axis indicates specific events.
A:
At “A”, VCC begins to increase. Also the VOUT voltage initially
increases but abruptly decreases when VCC reaches the level
(approximately 0.65 V) that activates the internal bias circuitry and
RESET is asserted.
B:
At “B”, VCC reaches the threshold level of VSH. At this point the
delay time, tPLH is initiated while VCC rises above VSH to its normal
operating level. The VOUT voltage remains in a low voltage state.
C:
At “C”, VCC is above VSL and the delay time elapses. At this
instant, the IC releases the hold on the VOUT reset. The reset output
then goes HIGH (assuming the reset pull-up resistor RPU is
connected to VCC). In a microprocessor based system these events
release the reset from the microprocessor, allowing the
microprocessor to function normally.
D-E:
At “D”, VCC begins to fall, causing VOUT to follow. VCC
continues to fall until the VSL undervoltage detection threshold is
reached at “E”. This causes a reset signal to be generated (VOUT
goes LOW).
E-F:
Between “E” and “F”, VCC continues to fall and then starts
rising.
F:
At “F”, VCC rises to the VSH level. Once again, the device
initiates the delay timer.
F-G:
VCC rises above VSH and returns to normal. At “G”, the delay
(tPLH) times out and once again, then it releases the hold on the
VOUT reset.
G-H:
At “G”, VCC is above the upper threshold and begins to fall,
causing VOUT to follow it. As long as VCC remains above the VSH,
no reset signal will be generated.
H:
At event “H”, VCC falls until the VSL undervoltage detection
threshold is reached. At this level, a RESET signal is generated and
VOUT goes LOW.
H-I:
Between “H” and “I”, VCC continues to fall and then starts to
rise rising. VCC rises to the VSH level at “I”, where the delay time is
again initiated.
I-J:
Between “I” and “J”, VCC rises above VSH to VCC normal and
then falls back to VSL level at “J”. At “J”, the reset signal is
reasserted before the delay time has elapsed. The time between “I”
and “J” is less than tPLH (reset delay time). Thus, the reset is not
released and the reset output remains LOW.
K–L:
Between “K” and “L”, VCC rises again back to normal
operating level causing the reset delay to be initiated at “K” and the
reset to be released at “L”.
M:
At “M”, VCC falls to VSL where the reset is asserted (VOUT
Reset goes LOW).
N:
At “N”, the VCC voltage has decreased until normal internal
circuit bias is unable to maintain a VOUT reset. As a result, VCC may
rise to less than 0.65 V. As VCC decreases further, the VOUT reset
also decreases to zero.
Vhys
tPLH
AB
C
D E
F
G
H
I
(RESET)
VOUT
V
tPLH
V
JK
L
M
N
< tPLH
VSH
VSL
VCC
SL01606
Figure 23. Timing diagram.
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