參數(shù)資料
型號(hào)： 935270978115
廠商： NXP SEMICONDUCTORS
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
封裝： 1.50 MM, PLASTIC, SOT-23, SOT-25, SO-5
文件頁(yè)數(shù)： 11/16頁(yè)
文件大?。?/td> 174K
代理商： 935270978115
Philips Semiconductors
Product data
NE56632-XX
Active-LOW system reset with adjustable delay time
2002 Mar 25
4
ELECTRICAL CHARACTERISTICS
Tamb = 25 °C, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
-XX
MIN.
TYP.
MAX.
UNIT
VS
Detection threshold
VCC = HIGH-to-LOW; RL = 4.7 k; S1=ON;
V
≤ 04 V
46
4.531
4.600
4.669
V
VOL ≤ 0.4 V;
Test Circuit 1 (Figure 27)
45
4.432
4.500
4.568
V
Test Circuit 1 (Figure 27)
44
4.334
4.400
4.466
V
43
4.235
4.300
4.365
V
42
4.137
4.200
4.263
V
31
3.053
3.100
3.147
V
30
2.955
3.000
3.045
V
29
2.856
2.900
2.944
V
28
2.758
2.800
2.842
V
27
2.659
2.700
2.741
V
20
1.970
2.000
2.030
V
19
1.871
1.900
1.929
V
Vhys
Hysteresis voltage
RL = 4.7 k; VCC = LOW-to-HIGH-to-LOW; S1 = ON; Test
Circuit 1 (Figure 27)
25
50
100
mV
VS/T
Detection threshold voltage
temperature coefficient
RL = 4.7 k; Tamb = –20 °C to +75 °C; S1 = ON;
Test Circuit 1 (Figure 27)
–
±0.01
–
%/
°C
VOL
LOW-level output voltage
VCC1 = VS(min) – 0.05 V; RL = 4.7 k; S1 = ON;
Test Circuit 1 (Figure 27)
–
0.2
0.4
V
ILO
Output leakage current
VCC1 = VCC2 = 10 V; S2 = ON; Test Circuit 1 (Figure 27)
–
±0.1
A
ICCL
Supply current (ON time)
VCC1 = VS(min) – 0.05 V; RL = ∞; Test Circuit 1 (Figure 27)
–
5.0
9.0
A
ICCH
Supply current (OFF time)
VCC1 = VS(typ)/0.85; RL = ∞; Test Circuit 1 (Figure 27)
–
3.0
5.0
A
tPLH
LOW-to-HIGH delay time
CL = 100 pF; RL = 4.7 k; CD = 10 nF (Note 1)
–
(Note 3)
–
ms
tPHL
HIGH-to-LOW delay time
CL = 100 pF; RL = 4.7 k; CD = 10 nF (Note 2)
–
(Note 3)
–
s
VOPL
Minimum operating
threshold voltage
RL = 4.7 k; VOL ≤ 0.4 V; S1 = ON;
Test Circuit 1 (Figure 27)
–
0.65
0.80
V
IOL1
Output current (ON Time 1)
VO = 0.4 V; RL = 0; VCC1 = VS(min) – 0.05 V;
VCC2 = 0.4 V; S2 = ON; Test Circuit 1 (Figure 27)
5
–
mA
IOL2
Output current (ON Time 2)
VO = 0.4 V; RL = 0; VCC1 = VS(min) – 0.05 V;
Tamb = –20 °C to +75 °C; S2 = ON;
Test Circuit 1 (Figure 27)
3
–
mA
NOTES:
1. tPLH:VCC = (VS(typ) – 0.4 V) to (VS(typ) + 0.4 V); tPLH is release delay time (Test Circuit 2, Figure 28).
2. tPHL:VCC = (VS(typ) + 0.4 V) to (VS(typ) – 0.4 V); tPHL is assertion delay time (Test Circuit 2, Figure 28).
3. See Table 1.
Table 1. NE56632-XX series typical delay time
–XX
tPLH
tPHL
46
195 ms
140
s
45
190 ms
140
s
44
185 ms
140
s
43
180 ms
140
s
42
175 ms
140
s
31
120 ms
120
s
30
115 ms
120
s
29
110 ms
120
s
28
105 ms
100
s
27
100 ms
100
s
20
65 ms
100
s
19
60 ms
100
s
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