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參數(shù)資料
| 型號： | 935270967115 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| 封裝： | 1.50 MM, PLASTIC, MO-178, SOT-23, SO-5 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 197K |
| 代理商： | 935270967115 |
Philips Semiconductors
Product data
NE56631-XX
Active-LOW system reset
2003 Feb 14
6
TECHNICAL DISCUSSION
The NE56631-XX is a Bipolar IC designed to provide power source
monitoring and a system reset function in the event the power sags
below an acceptable level for the system to operate reliably. The IC
is designed to generate a reset signal for a wide range of
microprocessor and other logic systems. The NE56631-XX can
operate at supply voltage up to 10 volts. The series includes several
devices with precision threshold reset voltage values of 1.9, 2.0, 2.7,
2.8, 2.9, 3.0, 3.1, 4.2, 4.3, 4.4, 4.5, 4.6 V. The reset threshold
incorporates a typical hysteresis of 50 mV to prevent erratic
reasserts from being generated. An internal fixed delay time circuit
provides a fixed power-on-reset delay of typically 20
s with a
guaranteed maximum delay of 60
s.
The output of the NE56631-XX utilizes an open collector topology,
which requires an external pull-up resistor to VCC. Though this may
be regarded as a disadvantage, it is advantageous in many
sensitive applications. Since the open collector output cannot source
reset current when both are operated from a common supply, the
NE56631-XX offers a safe interconnect to a wide variety of
microprocessors.
The NE56631-XX operates at low supply currents, typically 1.5
A,
while offering high precision of the threshold detection (
±3%).
Figure 9 is a functional block diagram of the NE56631-XX. The
internal reference source voltage is typically 0.65 V over the
temperature range. The reference voltage is connected to the
non-inverting input of the threshold comparator while the inverting
input monitors the supply voltage through a voltage divider network
made up of R1 and R2. The output of the comparator drives the
series base resistor, R3 of a common emitter amplifier, Q1. The
collector of Q1 is connected through R4 to the inverting terminal of
the op amp. The op amp output is connected to the series base
resistor, R5 of the output common emitter transistor, Q2. The
collector output of Q2 is connected to the non-inverting terminal of
the op amp which drives it.
When the supply voltage sags to the threshold detection voltage, the
resistor divider network supplies a voltage to the inverting terminal of
the threshold comparator which is less than VREF, causing the
output of the comparator to go to a HIGH state. This causes the
common emitter amplifier, Q1 to turn on pulling down the
non-inverting terminal of the op amp, which causes its output to go
to a HIGH state. This high output level turns on the output common
emitter transistor, Q2. The collector output of Q2 is pulled LOW
through the external pull-up resistor, thereby asserting the
Active-LOW reset.
The bipolar common emitter transistor, Q1and the op amp
establishes threshold hysteresis by turning on when the threshold
comparator goes to a HIGH state (when VCC sags to or below the
threshold level). With the output of Q2 connected to the
non-inverting terminal of the op amp, the non-inverting terminal of
the op amp has a level near ground at about 0.4 V when the reset is
asserted (Active-LOW). For the op amp to reverse its output, the
comparator output and Q1 must overcome the additional pull-down
voltage present on the op amp inverting input. The differential
voltage required to do this establishes the hysteresis voltage of the
sensed threshold voltage. Typically it is 50 mV.
When VCC voltage sags, and it is below the detection Threshold
(VSL), the device will assert a Reset LOW output at or near ground
potential. As VCC voltage rises from (VCC < VSL) to VSH or higher,
the Reset is released and the output follows VCC. Conversely,
decreases in VCC from (VCC > VSL) to VSL will cause the output to
be pulled to ground.
Hysteresis Voltage = Released Voltage – Detection Threshold
Voltage
VS = VSH – VSL
where:
VSH = VSL + VS
VSL = VSH – VS
When VCC drops below the minimum operating voltage, typically
0.65 V, the output is undefined and the output reset low assertion is
not guaranteed. At this level of VCC the output will try to rise to VCC.
3
4
R3
Q1
Q2
R5
VOUT
GND
OP1
CO1
R2
R1
5
VREF
VCC
SL01738
R4
Figure 9. Functional diagram.
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