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參數(shù)資料
| 型號(hào)： | 935270950115 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| 封裝： | 1.50 MM, PLASTIC, SOT-23, SOT-25, SO-5 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 238K |
| 代理商： | 935270950115 |
Philips Semiconductors
Product data
SA56615-XX;
SA56616-XX
CMOS system reset with adjustable delay time
2002 Mar 25
19
TIMING DIAGRAM
The Timing Diagram shown in Figure 75 depicts the operation of the
device. Letters A – K on the TIME axis indicate specific events.
A:
At “A”, VDD begins to increase. Initially, the VOUT voltage
increases but abruptly decreases when VDD reaches the level
(approximately 0.8 V) that activates the internal bias circuitry and
RESET is asserted.
B:
At “B”, VDD reaches the high side threshold level, VSH. At this
point the reset delay timer is initiated and VTCD, delay pin threshold
voltage begins to rise. VDD increases to its nominal operating level
without releasing the reset.
C:
At “C”, the delay pin threshold voltage is reached, and the IC
releases the hold on the VOUT reset. The reset output voltage goes
to VDD.
D–E:
At “D”, VDD begins to fall, causing the reset output to follow.
VDD continues to fall until the VSL, low side detection threshold level
is reached at “E”. This causes the a reset signal to be generated
(VOUT reset goes LOW).
E–F:
Between “E” and “F”, VDD starts rising.
F–G:
At “F”, VDD rises to VSH. Once again, the IC initiates the
reset delay timer and VTCD starts to rise until the delay pin threshold
level is reached and the IC releases the hold on the VOUT reset. At
“G”, the reset output VOUT goes to VDD.
G–H:
Between “G” and “H”, VOUT follow VDD. As long VDD
remains above VSH, no reset signal will be triggered. Before VDD
falls to the VSH threshold, it begins to rise, causing VOUT to follow it.
At “H” VDD returns to its nominal operating level.
J:
At “J” VDD falls until the VSL threshold point is reached. At this
level, a RESET signal is generated and VOUT goes LOW.
K: At “K”, the VDD voltage has decreased until normal internal circuit
bias is unable to maintain a VOUT reset. As a result, VOUT may rise
to less than 0.8 V. As VDD decreases further, VOUT reset also
decreases to zero.
A
K
BE
G
J
CD
F
H
VSH
VSL
VDD
VTCD
Vhys
OUT
t
VTCD
V
CD PIN
THRESHOLD
VOLTAGE
(VTHCD)
V
tD
SL01600
Figure 75. Timing diagram.
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