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參數(shù)資料
| 型號： | 935270922518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 固定正電壓單路輸出LDO穩(wěn)壓器 |
| 英文描述： | 5 V FIXED POSITIVE LDO REGULATOR, 0.5 V DROPOUT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SO-8 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 113K |
| 代理商： | 935270922518 |
Philips Semiconductors
Product data
SA56613-XX
5 V, 150 mA LDO and independent delayed RESET
2002 Mar 25
8
APPLICATION INFORMATION
Input capacitor
An input capacitor of
≥1 F is required to eliminate the AC coupling
noise. This capacitor must be located as close as possible to VIN or
GND pin (not more than 1 cm) and returned to a clean analog ground.
Any good quality ceramic, tantalum or film capacitor will work.
Output capacitor
Phase compensation is made for securing stable operation even if
the load current varies. For this reason, an output capacitor with
good frequency characteristics is needed. Set it as close to the
circuit as possible and make the wiring as short as possible.
The value of the output capacitance has to be at least 47
F
connected from VOUT to GND. When operating from sources other
than batteries, supply-noise rejection and transient response can be
improved by increasing the value of the input and output capacitors
and employing passive filtering techniques.
RESET output
The SA56613-XX has an Active-LOW RESET output. When VOUT of
the regulator rises above VSH, the upper detection threshold
voltage, the reset delay time is initiated. After the programmed delay
time elapses, RESET is released and goes HIGH. The time delay
can be set typically from 1 ms to 100 ms by connecting a time delay
capacitor from CD (pin 3) to ground (see Figure 9: RESET Delay
time versus CD, Delay Capacitor).
The RESET delay time (tPLH) can be approximated by the following
equation:
t
PLH + 10
5
C
Eqn. (1)
(Time is expressed in seconds, Capacitance in Farads.)
For example, for a delay capacitor, CD of 0.1 F (100 nF), tPLH is
approximately 10 ms.
When the regulator output Voltage falls to or below VSL, the lower
detection threshold voltage, the RESET output is asserted and it
goes to an Active-LOW state. This “LOW” transmission delay time is
typically 30
s with CD at 100 nF.
Reset hysteresis voltage
The reset hysteresis voltage,
VS is defined in the following
equation:
DV
S + VSH * VSL
Eqn. (2)
Hysteresis voltage is typically 50 mV. This small level of hysteresis
ensures that the reset will not dither when the regulator VOUT is noisy.
PCB layout
The component placement around the LDO should be done carefully
to achieve good dynamic line and load response. The input and
noise capacitors should be kept close to the LDO.
The rise in junction temperature depends on how efficiently the heat
is carried away from the junction to ambient. The junction to lead
thermal impedance is a characteristic of the package and fixed. The
thermal impedance between lead to ambient can be reduced by
increasing the copper area on the PCB. Increase the input, output
and ground trace area to reduce the junction-to-ambient impedance.
Power dissipation
The SA56613-XX maximum power dissipation depends on the
thermal resistance from the die junction to the ambient air. The
maximum power dissipation shown in Figure 10 is 650 mW at
ambient temperature of 25
°C. It is derated at 6.5 mW/°C above
25
°C.
Power dissipation of the device is PD = IOUT (VIN – VOUT). The
maximum power dissipation is:
Pmax
+
(T
j * Tamb)
(
q
JA)
Eqn. (3)
where
θJA = θJB + θBA, the junction-to-ambient thermal resistance, θJA
calculated from Figure 10 is 154
°C/W;
θJB is the thermal resistance from the die junction to PCB
material and copper traces;
θBA is the thermal resistance from the PCB material and copper
traces to the surrounding air.
The GND pin provides an electrical connection to ground and a path
for heat transfer from the device to the PCB and to the surrounding
air. To maximize heat transfer, connect the GND pin to a large
ground pad or ground plane.
The following example determines the maximum IOUT at
Tamb = 25 °C for VIN = 1 V.
I
OUT +
P
D
(V
IN * VOUT)
+ 650 mW
(12
* 5) +
92.8mA
Eqn. (4)
The maximum output current of the SA56613-XX is reduced as the
input voltage, VIN and the ambient temperature, Tamb increase.
LOGIC SYSTEM
SA56613-XX
1
2
3
5
4
VOUT
RESET
GND
CD
VIN
RESET
VCC
GND
COUT
4.7
F
VIN
0.1
F
CERAMIC
0.1
F
SL01729
Figure 12. Typical application circuit.
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