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參數(shù)資料
| 型號(hào)： | 935270920518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 固定正電壓?jiǎn)温份敵鯨DO穩(wěn)壓器 |
| 英文描述： | 5 V FIXED POSITIVE LDO REGULATOR, 0.5 V DROPOUT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SO-8 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | 935270920518 |
Philips Semiconductors
Product data
SA56613-XX
5 V, 150 mA LDO and independent delayed RESET
2002 Mar 25
7
TIMING DIAGRAM
The Timing Diagram in Figure 11 depicts the operation of the device.
Letters A-I on the Time axis indicates specific events.
A:
At “A”, VOUT abruptly begins to increase. Also the RESET
voltage initially increases but abruptly decreases when VOUT
reaches the threshold operating level (typically 0.65 V) that activates
the internal bias circuitry and RESET is asserted.
B:
At “B”,VOUT reaches the threshold level of VSH. At this point the
delay time, tPLH is initiated while VOUT rises above VSH to its normal
operating level of 5 V. The RESET voltage remains LOW.
C:
At “C”, VOUT is above VSL and the delay time, tPLH elapses. At
this instant, the device releases the hold on the RESET. The reset
output then goes HIGH. In a microprocessor based system these
events release the reset from the microprocessor, allowing the
microprocessor to function normally.
D-E:
At “D”, VIN falls below 5 V, causing VOUT to follow. VOUT
continues to fall until the VSL undervoltage detection threshold is
reached at “E”. This causes a reset signal to be generated (RESET
goes LOW).
E-F:
Between “E” and “F”, VOUT continues to fall and then starts
rising.
F:
At “F”, VOUT rises to the VSH level. Once again, the device
initiates the delay timer.
F-G:
VOUT rises above VSH and returns to normal 5 V output. At
“G”, the delay (tPLH) times out and once again, then it releases the
hold on the RESET and it goes HIGH.
G-H:
At “G”, VOUT is above the upper threshold and begins to fall,
causing RESET to follow it. As long as VOUT remains above the
VSL, no reset signal will be generated.
H:
At event “H”, VOUT falls until the VSL undervoltage detection
threshold is reached. At this level, a RESET signal is generated and
RESET goes LOW.
I:
At event “I”, VOUT has decreased until normal internal circuit bias
is unable to maintain a RESET. As a result, VCC may rise to less
than 0.65 V. As VCC decreases further, the VOUT reset also
decreases to zero.
AB
C
D E
F
G
H
I
VIN
VOUT
RESET
VSH
VSL
tPLH
10 V
5 V
0 V
5 V
VS
SL01651
Figure 11. Timing diagram.
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