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參數資料
| 型號： | 935270668112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-480-1, TVSOP-48 |
| 文件頁數： | 10/12頁 |
| 文件大小： | 102K |
| 代理商： | 935270668112 |
Philips Semiconductors
Product data
SSTV16857
14-bit SSTL_2 registered driver
with differential clock inputs
2002 Sep 27
7
PARAMETER MEASUREMENT INFORMATION
AC WAVEFORMS
VOL
tPLH
tPHL
OUTPUT
VREF
VIH
VIL
CLK
VOH
VREF
SW00836
Waveform 1. Propagation delay times
VREF
VIH
VIL
OUTPUT
tPHL
SW00837
VOH
VOL
RESET
Waveform 2. Propagation delay RESET to output.
VREF
VIH
VIL
INPUT
SW00339
tW
Waveform 3. Pulse duration
VREF
VIH
VIL
TIMING INPUT
SW00340
VREF
VIL
DATA INPUT
th
tsu
VIH
Waveform 4. Setup and hold times
TEST CIRCUIT
VTT
TEST POINT
CL = 30 pF
50
NOTES:
CL includes probe and jig capacitance
All input pulses are supplied by generators having the following characteristics:
PRR
≤ 10 MHz, ZO = 50 , tr ≤ 1.25 ns/V, tf 1.25 ns/V.
The outputs are measured one at a time with one transition per measurement.
VTT = VREF = VDDQ x 0.5
SW00838
Figure 1. Load circuitry
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