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參數(shù)資料
| 型號： | 935270479518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 固定正電壓單路輸出LDO穩(wěn)壓器 |
| 英文描述： | 2.5 V FIXED POSITIVE LDO REGULATOR, 0.5 V DROPOUT, PDSO7 |
| 封裝： | SOP-7 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 73K |
| 代理商： | 935270479518 |
Philips Semiconductors
Product data
SA57022-XX
500 mA LDO with ON/OFF control and Vref bypass
2001 Oct 03
5
APPLICATION INFORMATION
2
3
1
5
4
6
7
VOUT
NC
GND
BYPASS
VIN
SUB
ON/OFF
CIN = 1 F
CERAMIC
Cn = 470 pF
CERAMIC
VOLTAGE
INPUT
TO LOAD
COUT = 2.2 F
CERAMIC
SL01526
Figure 3. Typical application circuit.
Input capacitor
An input capacitor of 1.0
F (min) should be connected from VIN to
GND if there is more than 10 inches of wire between the regulator
and the AC filter capacitor, or if a battery is operated as the power
source. The capacitor should be less than 1 cm from the input pin.
Aluminum electrolytic or tantalum capacitor types can be used.
(Because many aluminum electrolytic capacitors freeze at
approximately –30
°C, solid tantalums are recommended for
applications operating below –25
°C.) When operating from sources
other than batteries, supply-noise rejection and transient response
can be improved by increasing the value of the input and output
capacitors and employing passive filtering techniques.
Output capacitor
Phase compensation is used to ensure stable operation even if load
current varies. For this reason, an output capacitor with good
frequency characteristics is needed. Set it as close to the circuit as
possible, with wires as short as possible. A 1.0
F capacitor from
VOUT to ground is recommended. The output capacitor should have
an ESR (effective series resistance) of 5.0
or less, and a resonant
frequency above 1.0 MHz.
Optional BYPASS capacitor
A 470 pF capacitor connected from the BYPASS input to ground
reduces noise present on the internal reference, which in turn
significantly reduces output noise. This capacitor must have low
leakage, because the pin is high impedance. If output noise is not a
concern, this pin may be left unconnected. Larger capacitor values
may be used, but results in a longer time period to rated output
voltage when power is initially applied.
ON/OFF
The regulator is fully enabled when a logic HIGH is applied to this
input. The regulator enters shutdown when a logic LOW is appplied
to this input. During shutdown, regulator output voltage falls to
zero,and supply current is reduced to 1.0
A max, and VOUT falls to
zero. For use as an always-on regulator, connect ON/OFF pin to the
supply voltage, as shown in Figure 3.
Optional BYPASS diode
If the voltage on the output pin rises above the input voltage, as
might happen in some applications, the overcurrrent will flow via
internal parasitic diodes from output to input. To prevent this,
connect a bypass diode between the output and input pins.
Thermal shutdown
Integrated thermal protection circuitry shuts the regulator off when
die temperature exceeds 150
°C. The regulator remains off until the
die temperature drops to approximately 140
°C.
Power dissipation
The amount of power the regulator dissipates is primarily a function
of input and output voltage, and output current. The following
equation is used to calculate worst case actual power dissipation:
P
D [ VIN(max) * VOUT(min)
I
LOAD(max)
Eqn. (1)
Where:
PD = worst case actual power dissipation
VIN(max) = maximum voltage on VIN
VOUT(min) = minimum regulator output voltage
ILOAD(max) = maximum output (load) current
The maximum allowable power dissipation, as shown in Equation (2),
is a function of the maximum ambient temperature (Tamb(max)), the
maximum allowable die temperature (125
°C), and the thermal
resistance from junction-to-air (Rth(j–a)).
Eqn. (2)
P
D(max) +
T
j(max) * Tamb(max)
R
th(j
*a)
The SUB (heat sink) pin must be connected to ground with a wide
trace.
PCB layout hints
The component placement around the LDO should be done carefully
to achieve good dynamic line and load response. The input and
noise capacitor should be kept close to the LDO. The rise in junction
temperature depends on how efficiently the heat is carried away
from the junction to ambient. The junction to lead thermal
impedance is a characteristic of the package and fixed. The thermal
impedance between lead to ambient can be reduced by increasing
the copper area on PCB. Increase the input, output and ground
trace area to reduce the junction-to-ambient impedance.
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