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參數(shù)資料
| 型號(hào)： | 935270464518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 4.40 MM, PLASTIC, SOT-530-1, VSOP-8 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | 935270464518 |
Philips Semiconductors
Product data
NE57607
Two-cell Lithium-ion battery protection with
overcurrent, over- and under-voltage protection
2001 Oct 03
3
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
TEMPERATURE RANGE
NE57607XDH
VSOP-8A
8-pin surface mount small outline package
–20 to +70
°C
NOTE:
The device has six protection parameter options, indicated by the X on the order code, and defined in the following table.
TYPICAL PROTECTION PARAMETERS IN THE NE57600 FAMILY
Tamb = 0 °C to 50 °C
Part Number
Overcharge
detection voltage
(V)
Overcharge detection
hysteresis voltage
(mV)
Over-discharge
detection voltage
(V)
Over-discharge
resumption voltage
(V)
Overcurrent
detection voltage
(mV)
NE57607Y
4.350
220
± 50
2.3
± 0.1
3.5
± 0.2
150
± 15
NE57607C
4.295
TBD
2.3
± 0.1
3.5
± 0.2
150
± 15
NE57607E
4.250
300
± 50
2.3
± 0.1
3.5
± 0.2
150
± 15
NE57607G
4.300
220
± 50
2.0
± 0.1
3.1
± 0.2
140
± 15
NE57607H
4.225
TBD
2.3
± 0.1
3.5
± 0.2
150
± 15
NE57607K
4.350
220
± 50
2.3
± 0.1
3.5
± 0.2
100
± 15
Part number marking
Each device is marked with a four letter code. The first three letters
in the top line of markings designate the product. The fourth letter,
represented by “x”, is a date code. The remaining markings are
manufacturing codes.
Part Number
Marking
NE57607YDH
AGDx
NE57607CDH
AGFx
NE57607EDH
AGHx
NE57607GDH
AGKx
NE57607HDH
AGLx
NE57607KDH
AGNx
PIN CONFIGURATION
SL01565
1
2
3
45
6
7
8
CF
DF
CS
GND
VC2
VCC
VC1
CDLY
TOP VIEW
Figure 2. Pin configuration.
PIN DESCRIPTION
PIN
SYMBOL
DESCRIPTION
1
CF
Charge FET drive pin, must have common
emitter NPN to drive FET gate.
Overcharge detection output pin
PNP open collector output
2
DF
Discharge control FET (N-ch) control output
pin.
3
CS
Overcurrent detection input pin.
Monitors discharge current equivalently by
the voltage drop between discharge FET
source and drain. Stops discharge when
voltage between CS pin and GND pin goes
above overcurrent detection threshold value,
and holds until load is released.
4
GND
Ground pin, or lower cell (C1) negative pin.
5
CDLY
Overcharge detection dead time setting pin.
Dead time can be set by adding a capacitor
between TD and GND pins.
6
VC1
Voltage input for positive terminal of bottom
cell (C10).
Connection pin for lower cell (C1) positive
electrode side and upper cell (C2) negative
electrode side.
7
VCC
Power supply input pin.
8
VC2
Voltage input for top terminal of upper cell
(C2).
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