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參數(shù)資料
| 型號： | 935270443118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | 12 2-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 84K |
| 代理商： | 935270443118 |
Philips Semiconductors
Product data
CBTD16213
24-bit level shifting bus exchange switch
with 12-bit output enables
2001 Nov 08
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = –40 to +85 °C
UNIT
Min
Typ1
Max
VIK
Input clamp voltage
VCC = 4.5 V; II = –18 mA
—
–1.2
V
VP
Output high pass voltage
See Figure 1.
—
V
I
Input leakage current
VCC = 0 V; VI = 5.5 V
—
10
A
II
Input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
—
±1
A
ICC
Quiescent supply current
VCC O = 0, VI = VCC or GND
—
1.5
mA
ICC
Additional supply current per
input pin2
VCC = 5.5 V, one input at 2.7 V,
other inputs at VCC or GND
—
2.5
mA
CI
Control pins
VI= 3 V or 0 V
—
4.5
—
pF
C O(O )
Port off capacitance B port
VO =3Vor0V; S0 S1 or S2 = VCC
—
11.5
—
pF
CIO(OFF)
Port off capacitance A port
VO = 3 V or 0 V; S0, S1, or S2 = VCC
—
11.5
—
pF
3
VCC =4 5V; V =0V; I =64mA
4
8
3
VCC = 4.5 V; V1 = 0 V; II = 64 mA
—
4
8
3
A to B or B to A
VCC = 4.5 V; V1 = 0 V; II = 30 mA
—
4
8
r 3
VCC = 4.5 V; V1 = 2.4 V; II = 15 mA
—
15
20
ron3
VCC =4 5V; V =0V; I =64mA
8
10
VCC = 4.5 V; V1 = 0 V; II = 64 mA
—
8
10
A1 to A2
VCC = 4.5 V; V1 = 0 V; II = 30 mA
—
8
10
VCC = 4.5 V; V1 = 2.4 V; II = 15 mA
—
24
30
NOTES:
1. All typical values are at VCC = 5 V, Tamb = 25 °C
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch.
On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
AC CHARACTERISTICS
GND = 0 V; tR; CL = 50 pF
SYMBOL
PARAMETER
FROM (INPUT)
TO
VCC = +5.0 V ±0.5 V
UNIT
SYMBOL
PARAMETER
FROM (INPUT)
(OUTPUT)
Min
Max
UNIT
t
Propagation delay1
A or B
B or A
—
0.25
ns
tpd
Propagation delay1
A1
A2
—
0.5
ns
t
Output enable time
S
A or B
3.2
9.6
ns
ten
to High and Low level
S0
A2 and B2
1.8
8.2
ns
t
Output disable time
S
A or B
2.1
8.5
ns
tdis
from High and Low level
S0
A2 and B2
1.4
7.5
ns
NOTES:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
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