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參數(shù)資料
| 型號： | 935270070157 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 56/56頁 |
| 文件大?。?/td> | 705K |
| 代理商： | 935270070157 |
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Philips Semiconductors
SC16C550
Universal Asynchronous Receiver/Transmitter (UART)
with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 04 — 13 March 2003
9 of 52
9397 750 11206
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
In sleep mode, XTAL2 is left oating.
6.
Functional description
The SC16C550 provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character (character orientated protocol). Data integrity is insured
by attaching a parity bit to the data character. The parity bit is checked by the receiver
for any transmission bit errors. The SC16C550 is fabricated with an advanced CMOS
process to achieve low drain power and high speed requirements.
The SC16C550 is an upward solution that provides 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C450. The SC16C550 is designed to work
with high speed modems and shared network environments that require fast data
processing time. Increased performance is realized in the SC16C550 by the larger
transmit and receive FIFOs. This allows the external processor to handle more
networking tasks within a given time. In addition, the four selectable levels of FIFO
trigger interrupt and automatic hardware/software ow control is uniquely provided for
maximum data throughput performance, especially when operating in a multi-channel
environment. The combination of the above greatly reduces the bandwidth
requirement of the external controlling CPU, increases performance, and reduces
power consumption.
The SC16C550 is capable of operation up to 3 Mbits/s with a 48 MHz external clock
input (at 5 V).
The rich feature set of the SC16C550 is available through internal registers.
Automatic hardware/software ow control, selectable receive FIFO trigger level,
selectable TX and RX baud rates, infrared encoder/decoder interface, modem
interface controls, and a sleep mode are some of these features. MCR[5] provides an
efcient hardware auto-ow control.
VCC
44
42
40
Power 2.5 V, 3.3 V or 5 V supply voltage.
VSS
22
18
20
Power Ground voltage.
IOW, IOW
20, 21
16, 17
18, 19
I
Write inputs. When either IOW or IOW is active (LOW or HIGH,
respectively) and while the UART is selected, the CPU is allowed to
write control words or data into a selected UART register. Only one of
these inputs is required to transfer data during a write operation; the
other input should be tied to its inactive level (i.e., IOW tied LOW or
IOW tied HIGH).
XTAL1
18
14
16
I
Crystal connection or External clock input.
XTAL2[1]
19
15
17
O
Crystal connection or the inversion of XTAL1 if XTAL1 is driven.
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
PLCC44 LQFP48 DIP40
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