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參數(shù)資料
| 型號(hào)： | 935270056518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 13/52頁 |
| 文件大?。?/td> | 680K |
| 代理商： | 935270056518 |
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Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 02 — 14 March 2003
20 of 49
9397 750 11192
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.
Register descriptions
Each register is selected using address lines A0, A1, A2, and in some cases, bits
from other registers. The programming combinations for register selection are shown
in Table 9.
[1]
MCR[7] can only be modied when EFR[4] is set.
[2]
Accessed by a combination of address pins and register bits.
[3]
Accessible only when LCR[7] is logic 1.
[4]
Accessible only when LCR is set to 10111111 (xBF).
[5]
Accessible only when EFR[4] = 1 and MCR[6] = 1, i.e., EFR[4] and MCR[6] are read/write enables.
[6]
Accessible only when CSA - CSD = 0, MCR[2] = 1, and loop-back is disabled (MCR[4] = 0).
Fig 13. Crystal oscillator connection.
002aaa169
X1
1.8432 MHz
C1
68 pF
C2
68 pF
XT
AL1
XT
AL2
Table 9:
Register map - read/write properties
A2
A1
A0
Read mode
Write mode
0
receive holding register (RHR)
transmit holding register (THR)
0
1
interrupt enable register (IER)
interrupt enable register
0
1
0
interrupt identication register (IIR)
FIFO control register (FCR)
0
1
line control register (LCR)
line control register
1
0
modem control register (MCR)[1]
modem control register[1]
1
0
1
line status register (LSR)
1
0
modem status register (MSR)
1
scratchpad register (SPR)
scratchpad register
0
divisor latch LSB (DLL)[2], [3]
divisor latch LSB[2], [3]
0
1
divisor latch MSB (DLH)[2], [3]
divisor latch MSB[2], [3]
0
1
0
enhanced feature register (EFR)[2], [4]
1
0
Xon1 word[2], [4]
1
0
1
Xon2 word[2], [4]
1
0
Xoff1 word[2], [4]
1
Xoff2 word[2], [4]
1
0
1
trigger level register (TLR)[2], [5]
trigger level register[2], [5]
1
FIFO ready register[2], [6]
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