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Philips Semiconductors
SC16C654/654D
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
8 of 52
9397 750 10985
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
A3, A4
20, 50
-
I
Address 3-4 select bits. When the 68 mode is selected, these pins are used
to address or select individual UARTs (providing CS is a logic 0). In the
16 mode, these pins are re-assigned as chip selects, see CSB and CSC. These
pins are not available on 64-pin packages which operate in the 16 mode only.
CDA, CDB,
CDC, CDD
9, 27,
43, 61
64, 18,
31, 49
I
Carrier Detect (Active-LOW). These inputs are associated with individual
UART channels A through D. A logic 0 on this pin indicates that a carrier has
been detected by the modem for that channel.
CLKSEL
30
-
I
Clock Select. The 1
× or 4× pre-scalable clock is selected by this pin. The 1×
clock is selected when CLKSEL is a logic 1 (connected to VCC) or the 4× is
selected when CLKSEL is a logic 0 (connected to GND). MCR[7] can override
the state of this pin following reset or initialization (see MCR[7]). This pin is not
available on 64-pin packages which provide MCR[7] selection only.
CS
16
-
I
Chip Select (Active-LOW). In the 68 mode, this pin functions as a multiple
channel chip enable. In this case, all four UARTs (A-D) are enabled when the
CS pin is a logic 0. An individual UART channel is selected by the data contents
of address bits A3-A4. when the 16 mode is selected (68-pin devices), this pin
functions as CSA (see denition under CSA, CSB). This pin is not available on
64-pin packages which operate in the 16 mode only.
CSA, CSB,
CSC, CSD
16, 20,
50, 54
7, 11,
38, 42
I
Chip Select A, B, C, D (Active-LOW). This function is associated with the
16 mode only, and for individual channels ‘A’ through ‘D’. When in 16 mode,
these pins enable data transfers between the user CPU and the
SC16C654/654D for the channel(s) addressed. Individual UART sections (A, B,
C, D) are addressed by providing a logic 0 on the respective CSA-CSD pin.
When the 68 mode is selected, the functions of these pins are re-assigned.
68 mode functions are described under their respective name/pin headings.
CTSA, CTSB,
CTSC, CTSD
11, 25,
45, 59
2, 16,
33, 47
I
Clear to Send (Active-LOW). These inputs are associated with individual
UART channels A through D. A logic 0 on the CTS pin indicates the modem or
data set is ready to accept transmit data from the SC16C654/654D. Status can
be tested by reading MSR[4]. This pin only affects the transmit or receive
operations when Auto CTS function is enabled via the Enhanced Feature
Register EFR[7] for hardware ow control operation.
D0-D2,
D3-D7
66-68,
1-5
53-55,
56-60
I/O
Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for
transferring information to or from the controlling CPU. D0 is the least
signicant bit and the rst data bit in a transmit or receive serial data stream.
DSRA,
DSRB,
DSRC, DSRD
10, 26,
44, 60
1, 17,
32, 48
I
Data Set Ready (Active-LOW). These inputs are associated with individual
UART channels, A through D. A logic 0 on this pin indicates the modem or data
set is powered-on and is ready for data exchange with the UART. This pin has
no effect on the UART’s transmit or receive operation.
DTRA,
DTRB,
DTRC, DTRD
12, 24,
46, 58
3, 15,
34, 46
O
Data Terminal Ready (Active-LOW). These outputs are associated with
individual UART channels, A through D. A logic 0 on this pin indicates that the
SC16C654/654D is powered-on and ready. This pin can be controlled via the
modem control register. Writing a logic 1 to MCR[0] will set the DTR output to
logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to
MCR[0], or after a reset. This pin has no effect on the UART’s transmit or
receive operation.
GND
6, 23,
40, 57
14, 28,
45, 61
I
Signal and power ground.
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
PLCC68 LQFP64