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| 型號： | 935270020128 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 667K |
| 代理商： | 935270020128 |
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Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs
and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 14 March 2003
27 of 47
9397 750 11204
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C2550 provides a temporary data register to store 8 bits of user
information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software ow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
1
MSR[1]
DSR [1]
Logic 0 = No DSR change (normal default condition).
Logic1=The DSR input to the SC16C2550 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
0
MSR[0]
CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C2550 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
Table 19:
Modem Status Register bits description…continued
Bit
Symbol
Description
Table 20:
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
Automatic CTS ow control.
Logic0=Automatic CTS ow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS ow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
6
EFR[6]
Automatic RTS ow control. Automatic RTS may be used for hardware ow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is lled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware ow control. RTS functions normally when
hardware ow control is disabled.
0 = Automatic RTS ow control is disabled (normal default condition).
1 = Enable Automatic RTS ow control.
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