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參數(shù)資料
| 型號(hào)： | 935269971118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-530-1, TSSOP-8 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 117K |
| 代理商： | 935269971118 |
Philips Semiconductors
Product data
PCK2002PL
533 MHz PCI-X clock buffer
2002 Oct 10
5
AC CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Tamb = –40 to +85 °C
UNIT
NOTES
MIN
TYP6
MAX
TH
CLK HIGH time
66 MHz
2
6.0
—
ns
TL
CLK LOW time
66 MHz
3
6.0
—
ns
TH
CLK HIGH time
140 MHz
2
2.9
—
ns
TL
CLK LOW time
140 MHz
3
3.0
—
ns
TR
Output rise slew rate
4
2.15
3.3
4.1
V/ns
TF
Output fall slew rate
4
2.5
3.3
4.4
V/ns
TPLH
Buffer LH propagation delay
5
1.8
2.9
3.4
ns
TPHL
Buffer HL propagation delay
5
1.8
2.8
3.4
ns
TSKW
Bus CLK skew
1
—
200
ps
TDDSKW
Device to device skew
1
—
500
ps
NOTES:
1. CLK skew is only valid for equal loading of all outputs.
2. TH is measured at 0.5 VDD as shown in Figure 2.
3. TL is measured at 0.35 VDD as shown in Figure 2.
4. TR and TF are measured as a transition through the threshold region 0.2 VDD to 0.6 VDD and 0.6 VDD to 0.2 VDD.
5. Input edge rate for these tests must be faster than 1 V/ns.
6. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
AC WAVEFORMS
VM = 50% VDD
CL = 10 pF
VOL and VOH are the typical output voltage drop that occur with the
output load.
BUF_IN
INPUT
VM
tPLH
tPHL
BUF_OUT
VM
SW00811
VDD
0.6 VDD
0.2 VDD
TR
0.6 VDD
0.2 VDD
TF
Figure 1. Load circuitry for switching times.
tp
th
tl
0.5 VDD
0.4 VDD
0.35 VDD
SW00812
Figure 2. Buffer Output clock
TEST CIRCUIT
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
VDD
140
140
SW00813
VDD
Figure 3. Load circuitry for switching times
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