參數(shù)資料
型號: 935269807112
廠商: NXP SEMICONDUCTORS
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: 7.50 MM, PLASTIC, MO-118, SOT-370-1, SSOP-48
文件頁數(shù): 10/12頁
文件大小: 91K
代理商: 935269807112
Philips Semiconductors
Product data
PCK2002
0–300 MHz I2C 1:18 clock buffer
2001 Jun 19
7
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.
All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating
current. The controller will read back the last written value.
Byte 0:
SDRAM Output active/inactive register
1 = enable; 0 = disable
BIT(S)
AFFECTED PIN
CONTROL FUNCTION
BIT CONTROL
BIT(S)
PIN NO.
PIN NAME
CONTROL FUNCTION
0
1
7
18
BUF_OUT7
Clock Output Disable
Low
Active
6
17
BUF_OUT6
Clock Output Disable
Low
Active
5
14
BUF_OUT5
Clock Output Disable
Low
Active
4
13
BUF_OUT4
Clock Output Disable
Low
Active
3
9
BUF_OUT3
Clock Output Disable
Low
Active
2
8
BUF_OUT2
Clock Output Disable
Low
Active
1
5
BUF_OUT1
Clock Output Disable
Low
Active
0
4
BUF_OUT0
Clock Output Disable
Low
Active
NOTE:
1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.
Byte 1:
SDRAM Output active/inactive register
1 = enable; 0 = disable
BIT(S)
AFFECTED PIN
CONTROL FUNCTION
BIT CONTROL
BIT(S)
PIN NO.
PIN NAME
CONTROL FUNCTION
0
1
7
45
BUF_OUT15
Clock Output Disable
Low
Active
6
44
BUF_OUT14
Clock Output Disable
Low
Active
5
41
BUF_OUT13
Clock Output Disable
Low
Active
4
40
BUF_OUT12
Clock Output Disable
Low
Active
3
36
BUF_OUT11
Clock Output Disable
Low
Active
2
35
BUF_OUT10
Clock Output Disable
Low
Active
1
32
BUF_OUT9
Clock Output Disable
Low
Active
0
31
BUF_OUT8
Clock Output Disable
Low
Active
NOTE:
1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.
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