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參數(shù)資料
| 型號： | 935269710112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | ALVC/VCX/A SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 79K |
| 代理商： | 935269710112 |
2003 Feb 06
2
Philips Semiconductors
Product specication
Quad 2-input NAND gate
74ALVC00
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC00 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
The 74ALVC00 provides the 2-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay inputs
nA, nB to output nY
VCC = 1.8 V; CL = 30 pF; RL =1k
2.8
ns
VCC = 2.5 V; CL = 30 pF; RL = 500
2.1
ns
VCC = 2.7 V; CL = 50 pF; RL = 500
2.6
ns
VCC = 3.3 V; CL = 50 pF; RL = 500
2.1
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per buffer
VCC = 3.3 V; notes 1 and 2
28
pF
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