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| 型號： | 935269256557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 145K |
| 代理商： | 935269256557 |
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2000 Nov 17
15
Philips Semiconductors
Preliminary specication
1394 SBP-2 link layer controller
SAA7356HL
Table 2
CmdFromMicro register denition (read/write)
Table 3
Sbp2Start register denition (read/write)
Table 4
CmdToMicro register denition (read/write)
BYTE
NUMBER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
Command(7:0)
BYTE
NUMBER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
Command(7:0)
BYTE
NUMBER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
Command(7:0)
8.3
Interrupt registers
As mentioned in the previous section, the communications
may be interrupt driven. To facilitate this there is one
InterruptReason and one InterruptEnable register. The
interrupt to the microcontroller is of the AND-OR type and
is asserted when any of the maskable interrupts are
enabled and active: to enable an interrupt, the
corresponding field in the InterruptEnable register must
be set to logic 1. Reading from the InterruptReason
register provides the un-masked value: this allows polling
if desired.
The InterruptEnable and InterruptReason register
definitions are shown in Tables 5 and 6 respectively.
In addition to these two registers, the microcontroller may
set the values in the InterruptReason register: this may
be used for setting initial conditions, for example. To set
the required bits, a logic 1 must be written to the flag
location in the InterruptSet register: writing a logic 0 to
any bit-field has no effect. The InterruptSet register
definition is given in Table 7.
It is recommended that only the InterruptReason.CmdClr
flag is set as InterruptReason.CmdMicro will cause a
maskable interrupt to be asserted to the microcontroller.
The definition of the InterruptReason, InterruptEnable
and the InterruptSet register fields are shown in Table 8.
Table 5
InterruptEnable register denition (read/write)
Table 6
InterruptReason register denition (read/write)
Table 7
InterruptSet register denition (write only, read via InteruptReason)
BYTE
NUMBER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
Reserved
CmdMicro
BusReset
CmdClr
BYTE
NUMBER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
Reserved
CmdMicro
BusReset
CmdClr
BYTE
NUMBER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
Reserved
CmdMicro
Reserved
CmdClr
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